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TPMC117 - TEWS TECHNOLOGIES

1. Bit Symbol Description Access Reset Value 31 2 Reserved always reads as 0 0 1 LCNT Load Counter W 0 Write 1 to load the counter with the value of the Counter Preload Register 0 RCNT Reset Counter W 0 Write 1 to reset the counter Table 3 8 Counter Command Register Commands are performed by writing 1 to the according bit 3 9 Digital Input Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 0 9 8 7 6 5 4 3 2 41 0 Reserved Digital Input Interrupt Control Digital Input Status LO N e T a ES o o o ae S S S SG SB ey Symbol Description Access Reset Value 31 12 Reserved always reads as 40 0 11 DIIC5 Digital Input Interrupt Control R W 0 10 DIIC4 Selects interrupt on rising or falling edge for corresponding 24V digital i 9 DIIC3 digita input 1 selects interrupt for rising edge 8 DIIC2 0 selects interrupt for falling edge 7 DIIC1 6 DIICO 5 DI5 These bits reflect the actual state of the digital 24V inputs R 4 In Reference Mode and Auto Reference Mode the digital 3 24V inputs used as reference inputs In all other modes the digital 24V inputs can be used as 2 DI2 general purpose inputs 1 DI 0 DIO Table 3 9 Digital Input Register TPMC117 User Manual Issue
2. ga ae d ina ces 41 6 3 3 9 Lateh on as 42 GEOP EMC IXgIMmETU 42 6 3 3 5 Beseton l i tc eee er 42 6 3 3 6 Reference dee RR 42 6 3 3 7 Auto Reference Mode u er ina RE EN ce n 43 6 3 3 8 Index M00822 uu 43 6 3 4 DatarRegister Lock teet eerie de deter teer d nep 44 6 4 Multiple Channel Read U U U u u uu uu uu u u 44 6 5 Interval TIME u 45 6 6 Isolated 24V Digital Inputs 12 uu u uu uu u uuu u u J 45 6 7 SSI Counter Input Filtering J U U U u u uu u u 45 7 HARDWARE INTERFACE SDN UU NIU Mn M AS GUN D M RIPE US ND VES Ee UNE EE 46 7 1 Encoder Counter Input Wiring U sisse sienne ente u nnn nnn u u u u u 46 7 4 4 Termination Resistor DIP Switches I n nennen nnn nnne nenn
3. 5 4 Embedded Company TECHNOLOGIES TPMC117 6 Channel SSI Incremental Encoder Counter Version 1 0 User Manual Issue 1 0 4 August 2014 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 40580 Fax 49 0 4101 4058 19 e mail info tews com www tews com TPMC117 10R 6 Channel SSI Incremental Encoder Counter Front panel I O TPMC117 20R 6 Channel SSI Incremental Encoder Counter P14 Back I O TPMC117 User Manual Issue 1 0 4 TEWS gt TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0 029 that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP RESET4 Access terms are described as W Write Only R Read Only RW Read Write R C Read Clear R S Read Set 2014 by TEWS TECHNOLOGIES GmbH All trademarks mentioned are property of the
4. l input Counter 0 Disabled 1 Enabled Table 6 11 Gate Mode In this mode an interrupt is generated if enabled when the gate is being closed I Input transition from 1 to 0 When a signal with constant frequency is connected to the A and B inputs this control mode can be used for impulse width measurements 6 3 3 5 Reset on An event on the l input resets clears the counter If the Single Cycle mode is active the event on the l input starts the counter The counter can also be reset by writing 1 to the Reset Counter RCNT bit in the Counter Command Register This control mode can be used to establish a known home or reference position in a mechanical system 6 3 3 6 Reference Mode This mode controls the counter with the isolated 24V digital reference input and the encoder index signal A specified reference input signal and a following index impulse produce a counter preload The host software must set the motion direction during such a reference access to backwards The following figure shows the two normal preload accesses An encoder motion area with eight index pulses and the corresponding reference input is described as an example Two different start positions 1a and 1b are shown Position 1a Direction is forward and the reference input is active The host software must move into the area where the reference input is inactive Now the direction must be changed The
5. Figure 8 1 Front Panel I O Connector Pin SSI Signal Counter Signal Pin SSI Signal Counter Signal CLK INO 36 CLK INO ENC_Bo DATAO 7 DATAO 10 CLK OUTO CLK OUTO GND_ ENC_A1 ENC_B1 11 Q O o o oa ya gt BR wo A O 2 1 CLK IN1 ENC_B1 DATA1 11 43 CLK OUT1 2 45 2 2 6 DATA2 12 47 CLK OUT2 CLK IN1 DATA1 CLK OUT1 1 2 2 12 CLK IN2 DATA2 CLK OUT2 25 CLK IN5 ENC_B5 59 CLK IN5 ENC_B5 TPMC117 User Manual Issue 1 0 4 Page 50 of 52 TEWS 2 TECHNOLOGIES SSI Signal Counter Signal SSI Signal exo o 24V Digital Input 0 GND 30 24V Digital Input 1 GND 31 24V Digital Input 2 GND Counter Signal ENC_I5 32 24V Digital Input 3 24V Digital Input 3 GND 33 24V Digital Input 4 24V Digital Input 4 GND 34 24V Digital Input 5 24V Digital Input 5 GND Table 8 1 Pin Assignment Front I O Connector TPMC117 User Manual Issue 1 0 4 Page 51 of 52 8 2 P14 Back I O Connector The TPMC117 P14 Back I O connector is Standard 64 pin Mezzanine Connector Pin SSI Signal Counter Signal 1 0 3 CLK INO 0 5 10 7 CLK OUT0 9 ENC_A1 11 CLK IN1
6. For PCI Memory Space mapping starting at bit location 4 the first bit set to 1 determines the size of the required PCI Memory Space size For PCI Expansion ROM mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the PCI9030 is requesting a 32 byte space address bits 4 0 are not part of base address decoding 5 Determine the base address and write the base address to the PCI9030 PCI Base Address Register For PCI Memory Space mapping the mapped address region must comply with the definition of bits 3 1 of the PCI9030 PCI Base Address Register After programming the PCI9030 PCI Base Address Registers the software must enable the PCI9030 for PCI I O and or PCI Memory Space access in the PCI9030 PCI Command Register Offset 0x04 To enable PCI I O Space access to the PCI9030 set bit 0 to 1 To enable PCI Memory Space access to the PCI9030 set bit 1 to 1 Offset in Config Description Usage 0x10 9030 LCR s Used 0x14 PCI9030 LCR s I O Used 0x18 PCI9030 Local Space 0 Used 0x1C PCI9030 Local Space 1 Not used 0x30 Expansion ROM Not used Table 4 2 PCI9030 PCI Base Address Usage TPMC117 User Manual Issue 1 0 4 Page 29 of 52 TEWS amp TECHNOLOGIES 4 2 Local Configuration Register LCR After reset the PCI9030 Local Co
7. TECHNOLOGIES 6 2 2 SSI Listen only Mode In Listen only Mode a TPMC117 channel listens to an existing SSI interface to observe the data transfer Both the SSI clock and data signals are inputs to the TPMC117 Absolute Encoder TPMC117 Listen Only CLKINO 2 CLKINO 36 lt DATAO 3 Figure 6 3 Wiring Example Channel 0 Listen only Mode This mode is enabled when the Interface Control in the Global Control Register is set to 01 and the MODE bit in the Control Register is set to 1 Register Bit Setting Global Control Register ICx 01 Control Register MODE d Table 6 3 SSI Listen only Mode Selection In the Control Register the SSI interface must be set up conforming to the settings required of the observed SSI interface Register Symbol Setting Control Register X BC Number of data bits CODE Binary Gray Code ZB Additional Zero Bit EO Even Odd Parity PAR Parity detection CR Table 6 4 SSI Listen only Setup TPMC117 User Manual Issue 1 0 4 Page 37 of 52 TEWS gt TECHNOLOGIES The clock rate setting in the Control Register is don t care the clock rate of the observed SSI interface will be detected automatically After the Control Register is set up the channel listens indicated by Busy 1 A d
8. Value of 1 resets the PCI9030 and issues a reset to the Local Bus LRESETo asserted PCI9030 remains in this reset condition until the PCI Host clears this bit The contents of the PCI9030 PCI and Local Configuration Registers are not reset The PCI9030 PCI Interface is not reset TPMC117 User Manual Issue 1 0 4 Page 32 of 52 5 Configuration Hints 5 1 Big Little Endian PCI Bus Little Endian Byte 0 AD 7 0 Byte 1 AD 15 8 Byte 2 AD 23 16 Byte 3 AD 31 24 Big Endian Little Endian 32 Bit 32 Bit Byte 0 07 0 Byte 0015 Byte 2 023 16 Byte 9 01 24 16 Bit upper lane 16 Bit Byte 0 07 0 Byte 015 8 16 8 Bit upper lane 8 Bit Byte 0 07 0 8 Bit lower lane Byte 0 D 7 0 Table 5 1 Local Bus Little Big Endian TPMC117 User Manual Issue 1 0 4 TEWS gt TECHNOLOGIES Every Local Address Space 0 3 and the Expansion ROM Space can be programmed to operate in Big or Little Endian Mode Page 33 of 52 Standard use of the TPMC117 Local Address Space 0 Local Address Space 1 Local Address Space 2 Local Address Space 3 Expansion ROM Space TEWS E TECHNOLOGIES 32 bit bus in Little Endian Mode not used not used not used not used To change the Endian Mode use the Local Configuration Registers for the corresponding Space Bit 24 of the according register sets the mode A value of 1 indicates Big Endian and a val
9. Load I or Reset on I mode The counter will stop when it creates a borrow or a carry TPMC117 User Manual Issue 1 0 4 Page 40 of 52 TEWS gt TECHNOLOGIES 6 3 3 Index Control Modes The Index Control Mode determines how events on the l input are interpreted With the exception of the Gate on mode all modes react on a level change on the l input Due to the digital input filtering a change in the input level is only detected when the input line is stable for at least 100ns The following table gives an overview of the index control mode events Index Control Mode Polarity high active low active POL 0 POL 1 No I Control Load Rising edge Falling edge Latch on Rising edge Falling edge Gate on High level Low Level Reset on Rising edge Falling edge Reference Mode Rising edge Falling edge Auto Reference Mode Rising edge Falling edge Index Mode Rising edge Falling edge TPMC117 User Manual Issue 1 0 4 Table 6 9 Index Control Mode events The control modes Reference Mode Auto Reference Mode and Index Mode are only valid when the input mode is quadrature count They control the counter with the encoder index input in cooperation with a reference switch connected to the isolated 24V digital input An interrupt can be generated on a control mode event This is only available for the Load Latch Gate and Reset on modes
10. u 19 3 8 Counter Command Register 19 3 9 Digital Input Register 20 3 10Interval Timer Control Register 21 3 11 Interval Timer Preload 21 3 12Interval Timer Data Register 1 21 u u u u u uu u u antenna nena 22 3 13Global Control Register 22 3 14Interrupt Enable Register J l 24 3 15 Interrupt Status Register J u u uu uu u u u 25 3 16 Test uuu M 26 4 PCISUSU TARGET CHIP 28 4 1 PCI Configuration Registers PCR U 28 4 1 1 PGOI9030 Header Irene u ee tec Eta dada eh a 28 4 1 2 PCI Base Address 29 4 2 Local Configuration Register LCR U u uu u u u 30 4 3 Configuration ccccnccetesectcocceescqeentecdeccccaccaresneateoccuezenersteadesciccseqcedSncuedsciezsnceedencevecers 31 4 4 Local Software Heset 1 neadan a
11. 1 13 DATA1 11 15 CLK OUT1 17 ENC_A2 19 CLK IN2 ENC_B2 21 DATA2 12 23 CLK OUT2 25 ENC_A3 27 CLK IN3 ENC_B3 29 DATA3 31 CLK OUT3 33 ENC_A4 35 CLK IN4 ENC_B4 37 DATA4 14 39 CLK OUT4 41 ENC_A5 43 CLK IN5 ENC_B5 45 DATA5 47 CLK OUT5 49 GND 1 51 GND 1 53 24V Digital Input 0 55 24V Digital Input 1 57 24V Digital Input 2 59 24V Digital Input 3 61 24V Digital Input 4 63 24V Digital Input 5 TEWS gt TECHNOLOGIES Pin N 4 14 22 6 30 36 8 a Q gt N ojoj AJIN O ine 4 6 48 SSI Signal Counter Signal GND GND 24V Digital Input 0 GND 24V Digital Input 1 GND 24V Digital Input 2 GND 24V Digital Input 3 GND 24V Digital Input 4 GND 24V Digital Input 5 GND Table 8 2 Pin Assignment Front I O Connector TPMC117 User Manual Issue 1 0 4 Page 52 of 52
12. 1 SSI Timing Example When not transmitting the clock and data lines are high To read out the positional data of an absolute encoder the controller transmits a pulse train on the CLOCK line The first falling edge of CLOCK latches the positional data of the absolute encoder At the first rising edge of CLOCK the absolute encoder presents the most significant bit on the DATA line On each subsequent rising edge in the CLOCK pulse train the next bit in order is transmitted to the controller In addition to the data bits the absolute encoder can transmit a parity bit for error detection As an option a zero bit can be placed between the data and the parity bit After all bits are transmitted the absolute encoder holds the data line low for 10 30us recovery time tm After that the absolute encoder is ready for a new transmission A new transmission must not started before The maximum achievable baud rate depends on the cable length Cables are assumed to be twisted pair and screened Cable length m Baud rate KHz 50 400 100 300 200 200 400 100 TPMC117 User Manual Issue 1 0 4 Page 35 of 52 TEWS gt TECHNOLOGIES 6 2 SSI Mode 6 2 1 Standard SSI Interface Controller Mode In this mode a TPMC117 channel operates as a standard SSI interface controller The SSI clock is an output and data signal is an input to the TPMC117 TPMC117
13. 1 0 4 Page 20 of 52 TEWS gt TECHNOLOGIES 3 10 Interval Timer Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 0 0 010 010 0 010 010 010 0 010 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 2 Symbol Description Access Reset Value 31 3 Reserved always reads as 40 0 2 1 ITDIV Interval Timer Clock Divider RW 0 Value Mode 0 0 8 MHz 0 1 4 MHz 1 0 2 MHz 1 1 1 MHz 0 ITEN Interval Timer Enable R W 0 0 disables the Interval Timer 1 enables the Interval Timer Table 3 10 Interval Timer Control Register 3 11 Interval Timer Preload Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 15 14 13 12 11 40 9 8 7 6 5 4 3 2 1 0 Interval Timer Preload Register ITPRE Bit Symbol Description Access Reset Value 31 16 Reserved always reads as 40 0 15 0 ITPRE Interval Timer Preload Register R W 0 Table 3 11 Interval Timer Preload Register TPMC117 User Manual Issue 1 0 4 Page 21 of 52 3 12 Interval Timer Data Register TEWS gt TECHNOLOGIES Bit 31 30 29 28 2
14. Index Control Mode No Control Mode Interrupt generation No interrupt Load Mode Latch Mode Control mode event Reset Mode Gate Mode Gate closed Table 6 10 Index control mode interrupt generation 6 3 3 1 No I Control In this mode the l input is ignored 6 3 3 2 Load An event on the l input loads the counter with the content of the Counter Preload Register If the Single Cycle mode is active the event on the l input will start the counter The counter can also be preloaded by writing 1 to the Counter LCNT bit in the Counter Command Register This control mode can be used to establish a known reference position in a mechanical system Page 41 of 52 TEWS gt TECHNOLOGIES 6 3 3 3 Latch on An event on the l input loads and locks the Data Register with the actual counter value see chapter Data Register Lock for details It will remain latched until the Data Register is read or the latch is released with the CDLT bit in the Status Register When a Latch on I event occurs while the Data Register Lock is still active the data in the Data Register will be retained and the Data Register Lock Overflow OVFL will be set to indicate that data was lost This control mode can be used to capture a position in a mechanical system 6 3 3 4 Gate on The signal level on the l input enables or disables counting Remember that in this mode the l input is level sensitive
15. The interrupts are acknowledged by writing a 1 to the 42 CISTAO according bit 11 MISTAS5 Pending Match Interrupts Read R C 0 10 MISTA4 Interrupt acknowledge Write 9 MISTA3 On a read access these bits indicate the channels with pending match interrupts A 1 indicates a pending interrupt 8 MISTA2 The interrupts are acknowledged by writing a 1 to the 7 MISTA1 according bit 6 MISTAO 5 SISTA5 Pending SSI Interrupts Read R C 0 4 SISTA4 Interrupt acknowledge Write 3 SISTA3 On read access these bits indicate the channels with pending SSI interrupts A 1 indicates a pending interrupt 2 SISTA2 The interrupts are acknowledged by writing 1 to the 1 SISTA1 according bit 0 SISTAO Table 3 15 Interrupt Status Register 3 16 Test Register This register allows quick testing of the RS422 TTL in and outputs To check the digital input levels read the Digital Input Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SSI Clock Outputs Channel z 9 3 9 9 1 2 oo o ojo Oo o S 28 8 Bit 15 14 13 12 44 40 9 8 7 6 5 4 3 2 1 0 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 0 zx elia 2 s m S mx m lt TPMC117 User Manual Issue 1 0 4 Page 26 of 52 TEWS 2 TECHNOLOGIES Bit Symbol Description Ac
16. polarity Bit Input Polarity 26 A 0 high active 1 low active 27 B 0 high active 1 low active 28 0 high active 1 low active 25 23 ICM Index Control Mode R W 000 2 0 The Index Control Mode determines how the counter interprets events on the l input Reference modes are only valid when Input Mode Quadrature Count ICM Mode None Reference Mode 000 Ignore l input 001 Load on 010 Latch on 011 Gate 100 Reset on Reference Modes 101 Reference mode 110 Auto reference mode 111 Index mode See chapter 6 3 3 Index Control Modes for details 22 21 SCM Special Count Mode R W 00 SCM Mode 00 special mode active cycling counter 01 Divide by N 10 Single Cycle See chapter 6 3 2 Special Count Modes for details 20 19 CLKDIV Internal Clock Prescaler R W 00 1 0 CLKDIV Prescaler Clock frequency 00 1x 32 MHz 01 2 16 MHz 10 4x 8 MHz 11 8x 4 MHz TPMC117 User Manual Issue 1 0 4 Page 14 of 52 TEWS 2 TECHNOLOGIES Bit Symbol Description Access Reset Value 18 16 INPUT Counter Input Mode RAN 000 2 0 The Input Mode determines the input source and how the counter interprets these input signals The Quadrature mode can be used with a 1x 2x or 4x resolution multiplier INPUT Input Mode Inp
17. the SSI channel that takes the longest time to complete a conversion If only counter channels are read an interrupt is not necessary because the counter data is instantly available 6 5 Interval Timer The interval timer is a 16 bit preloadable counter with a programmable clock rate On activation the counter loads from the Interval Timer Preload Register und starts counting down When the counter reaches zero it generates an interrupt if enabled is automatically preloaded again and continues counting With the 16 bit preload register and the programmable clock interval interval times up to 65ms are possible Calculate the interval times using the following formula Interval Time Value of Interval Timer Preload Register Clock period ITDIV Clock Frequency Clock Period 00 8 MHz 125ns 01 4 MHz 250ns 10 2 MHz 500ns 11 1 MHz ius Table 6 13 Interval Timer Clock Periods The interval timer can be used as a reference timer in closed loop applications or as a trigger for a multiple channel read 6 6 Isolated 24V Digital Inputs The TPMC117 offers one isolated digital 24V input per channel The inputs are electronically debounced Each digital 24V input can generate an interrupt triggered on rising or falling edge Depending on the selected counter reference mode the input can be used as a general purpose input or as a reference input 6 7 SSI Counter Input Filtering To avoid false counts caused by noi
18. 0 4 PAR Encoder with parity If encoder provides a parity bit RW 0 1 detect parity errors 0 do not detect parity errors no parity bit TPMC117 User Manual Issue 1 0 4 Page 15 of 52 TEWS gt TECHNOLOGIES Bit Symbol Description Access Reset Value 3 CR3 Clock Rate for encoder serial clock speed R W 0 2 2 The clock be programmed in steps of 1us in the range of 1 to 15 A value of 0 for the clock rate will stop the operation 1 CRI of the SSI interface 0 CRO The Listen only Mode will ignore the Clock Rate setting in this mode the Clock Rate will be detected automatically Table 3 3 Control Register Note that a value of 0x00 a value from 0x21 to for BC5 BCO is not valid and will stop the operation of the SSI Interface 3 4 Data Register Bit Symbol Description Access Reset Value 31 0 Data Register R S 0 Table 3 4 Data Register When the channel is disabled the Data Register returns 0x00000000 on read accesses 3 4 1 Data Register in SSI Mode The serial data of the absolute encoder is shifted into the Data Register In Standard SSI Interface mode a write access to the Data Register initiates a data transfer from the absolute encoder independently of the other channels In Listen only SSI Interface mode a read access to the Data Register sets the Busy bit to 1 and the chan
19. 0 4 Page 48 of 52 TEWS gt TECHNOLOGIES TPMC117 Absolute Encoder System Ground Figure 7 6 Clock Output Wiring with Differential Receiver Input 116 an isolated input ground that can not be used as the clock output ground reference 7 3 Digital Input Characteristics The TPMC1 17 offers one digital 24V input per channel which is galvanically isolated by optocouplers A high performance input circuit ensures a defined switching point and polarization protection against confusing the pole The inputs are electronically debounced Each of the four digital 24V inputs can generate an interrupt triggered on rising or falling edge Depending on the selected reference mode the input can be used as general purpose input or as reference input Parameter Unit Typical Input isolation Optocoupler as galvanic isolation Input voltage V 24 Input current mA 4 2 at 24V input voltage Switching level V 12 min 7 5 max 14 Table 7 3 Digital Input Characteristics VCC DIN 24V 0 1 GDIN Figure 7 7 Digital Input Wiring TPMC117 User Manual Issue 1 0 4 Page 49 of 52 TEWS gt TECHNOLOGIES 8 Pin Assignment I O Connector 8 1 Front Panel I O Connector The TPMC117 front panel I O connector is a HD68 SCSI 3 type female connector e g AMP 787082 Pin 34 Pin 1 UT ese Wasa 68 35
20. 00 Not used 0x3C Chip Select 0 Base Address 0x0000_0081 Chip Select Local Space 0 0x40 Chip Select 1 Base Address 0x0000_0000 Not used 0x44 Chip Select 2 Base Address 0x0000_0000 Not used 0x48 Chip Select 3 Base Address 0x0000_0000 Not used 0x4C Interrupt Control Status 0x0041 Local IRQ1 amp PCI IRQ enabled Ox4E EEPROM Write Protect Boundary 0x0030 Standard write protection 0x50 Miscellaneous Control Register 0x0078 0000 Retry delay max 0x54 General Purpose I O Control 0 0000 0001 No GPIO 0x70 Hidden1 Power Management data 0x0000 0000 Not used select 0x74 Hidden 2 Power data 0x0000_0000 Not used scale Table 4 3 PCI9030 Local Configuration Register TPMC117 User Manual Issue 1 0 4 Page 30 of 52 TEWS gt TECHNOLOGIES 4 3 Configuration EEPROM After power on or PCI reset the PCI9030 loads initial configuration register data from the on board configuration EEPROM The configuration EEPROM contains the following configuration data e Address 0x00 to 0x27 PCI9030 PCI Configuration Register Values e Address 0x28 to 0x87 PCI9030 Local Configuration Register Values e Address 0x88 to OxFF Reserved See the PCI9030 Manual for more information Address Offset 0x00 0x02 0x04 0x06 0x08 0x0C 0x00 0x0075 0 1498 0 0280 0 0000 0 1180 0 0000 s b 0x1498 0x10 Ox0000 0x0040 0x0000 0 0100 0x4801 0 4801 0 0000 0 0000 0x20 Ox0000 0x4C06 0x0000 0 0003 OxOFFF OxFFO0 0 0000 0 0000 0x30 00
21. 000 0x0000 0 0000 0x0000 0 0000 0x0000 0x0000 0 0001 0x40 Ox0000 0x0000 0 0000 0 0000 0x0000 0x0000 0x0000 0 0000 0x50 0x4180 0x0020 0x0000 0 0000 0x0000 0x0000 0 0000 0x0000 0x60 Ox0000 0x0000 0 0000 0x0081 0 0000 0x0000 0x0000 0 0000 0x70 Ox0000 0x0000 0 0030 0x0041 0 0078 0x0000 0x0000 0 0240 0x80 0 0000 0x0000 0 0000 0 0000 OxFFFF OxFFFF OxFFFF 0x90 OxFFFF OxFFFF OxFFFF OxFFFF OxAO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxDO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxEO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFO0 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF Table 4 4 Configuration EEPROM TPMC1 17 Subsystem ID Value Offset 0 0 TPMC117 10R 0x000A TPMC117 20R 0x0014 TPMC117 User Manual Issue 1 0 4 Page 31 of 52 TEWS gt TECHNOLOGIES 4 4 Local Software Reset The PCI9030 Local Reset Output LRESETo is used to reset the on board local logic The PCI9030 local reset is active during PCI reset or if the PCI Adapter Software Reset bit is set in the PCI9030 local configuration register CNTRL offset 0x50 CNTRL 30 PCI Adapter Software Reset
22. 000 4 2 Air Gap Discharge Number of Isolated Digital Inputs 6 digital inputs reference input or general purpose input depending on mode Maximum Input Frequency Input Voltage 5 MHz 24V DC typical Input Current 4 2 24V input voltage Input Switching Level 12V typical 7 5V minimum 14V maximum Interval Timer Connector Physical Data Programmable with timing intervals up to 65ms TPMC117 10R HD68 SCSI 8 type connector e g AMP 787082 TPMC117 20R P14 Back I O Power Requirements 160 mA typical 5V DC 10 mA typical 3 3V DC Temperature Range Operating 40 C to 85 C Storage 40 C to 85 C MTBF 330 000 h MTBF values shown are based on calculation according to MIL HDBK 217F and MIL HDBK 217F Notice 2 Environment Gg 20 C The MTBF calculation is based on component FIT rates provided by the component suppliers If FIT rates are not available MIL HDBK 217F and MIL HDBK 217F Notice 2 formulas are used for FIT rate calculation Humidity 5 95 non condensing Weight 774 Table 2 1 Technical Specification TPMC117 User Manual Issue 1 0 4 Page 10 of 52 TEWS gt TECHNOLOGIES 3 Local Space Addressing 3 1 PCI9030 Local Space Configuration The local on board addressable regions are accessed from the PCI side by using the PCI9030 local spaces PCI9030 PCI9030 PCI Size Port Endian Description Local PCI Base Address Spac
23. 7 26 25 24 23 22 21 20 19 18 17 16 Reserved Bit 15 14 43 12 11 0 9 8 7 6 5 4 3 2 1 0 Interval Timer Data Register ITDR Bit Symbol Description Access Reset Value 31 16 Reserved always reads as 0 0 15 0 ITDR Interval Timer Data Register R W 0 This register contains the actual Interval Timer Value Table 3 12 Interval Timer Data Register 3 13 Global Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MCR Manual oye op MEM EA Pag ra M ric gt gt Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Counter Preload Interface Control 3 5 ee 3 T EI EIE IC5 4 IC3 IC2 IC1 ICO Bit Symbol Description Access_ Reset Value 31 27 Reserved always reads as 40 0 26 MCRTR Multiple Channel Read Trigger W 0 By writing 1 to this bit a Multiple Channel Read is triggered This is only valid for channels which are already enabled for a Multiple Channel Read Do not set the SLx bits and the MCRTR bit on the same write access TPMC117 User Manual Issue 1 0 4 Page 22 of 52 TEWS 2 TECHNOLOGIES 25 Multiple Channel Read Status
24. Controller Absolute Encoder CLKO 4 CLOCK CLKO 38 CLOCK DATAO 3 DATA 4 L 4 id DATAO 37 DATA Jie See hi ee Figure 6 2 Wiring Example Channel 0 SSI Interface Controller Mode This mode is enabled when the Interface Control in the Global Control Register is set to 01 and the MODE bit in the Control Register is set to 0 Register Symbol Setting Global Control Register ICx 01 Control Register X MODE 0 Table 6 1 SSI Standard Mode Selection In the Control Register the SSI interface must be set up conforming to the settings required of the connected absolute encoder Register Symbol Setting Control Register X BC Number of data bits CODE Binary Gray Code ZB Additional Zero Bit EO Even Odd Parity PAR Parity detection CR Clock Rate Table 6 2 SSI Setup A data transfer is initiated by a write to the Data Register The SSI interface controller then generates a clock burst on which the absolute encoder returns its positional data The SSI Controller receives this data processes it parity check gray to binary code conversion and indicates the end of the data transfer with the deassertion of the Busy bit If enabled an interrupt is asserted and the positional data can be read in the Data Register In this mode the Read Error status bit is always read as 0 TPMC117 User Manual Issue 1 0 4 Page 36 of 52 TEWS gt
25. MINATION RESISTOR DIP 5 5 46 SINGLE ENDED INPUT WIRING u 47 DIFFERENTIAL INPUT 48 CLOCK OUTPUT WIRING WITH OPTOCOUPLER INPUT ee 48 CLOCK OUTPUT WIRING WITH DIFFERENTIAL RECEIVER 49 DIGITAE INPUT WIRING u ua uuu su eerta cr h een 49 FRONT PANEL I O CGONNEGTOR et ett 50 Page 6 of 52 TABLE 2 1 TABLE 3 1 TABLE 3 2 TABLE 3 3 TABLE 3 4 TABLE 3 5 TABLE 3 6 TABLE 3 7 TABLE 3 8 TABLE 3 9 TABLE 3 10 TABLE 3 11 TABLE 3 12 TABLE 3 13 TABLE 3 14 TABLE 3 15 TABLE 3 16 TABLE 4 1 TABLE 4 2 TABLE 4 3 TABLE 4 4 TABLE 5 1 TABLE 6 1 TABLE 6 2 TABLE 6 3 TABLE 6 4 TABLE 6 5 TABLE 6 6 TABLE 6 7 TABLE 6 8 TABLE 6 9 TABLE 6 10 TABLE 6 11 TABLE 6 12 TABLE 6 13 TABLE 7 1 TABLE 7 2 TABLE 7 3 TABLE 8 1 TABLE 8 2 TPMC117 User Manual Issue 1 0 4 List of Tables TECHNICAL SPECIFICATION PCI9030 LOCAL SPACE CONFIGURATION LOCAL REGISTER ADDRESS SPACE CONTROL REGISTER DATA REGISTER SSI STATUS REGISTER COUNTER PRELOAD REGISTER COUNTER COMPARE REGISTER COUNTER COMMAND REGISTER DIGITAL INPUT REGISTER INTERVAL TIMER CONTROL REGISTER INTERVAL TIMER PRELOAD REGISTER INTERVAL TIMER DATA REGISTER GLOBAL CONTROL REGISTER INTERRUPT ENABLE REGISTER INTER
26. R C 0 This bit indicates pending Multiple Channel Read data When a SSI channel is enabled for Multiple Channel Read it takes time for the conversion to complete This bit indicates that the conversions of all enabled channels are complete 1 Multiple Channel Read Data is valid for all enabled channels 0 The Data Registers of all enabled channels have been read out To reset a multiple channel read sequence write 1 to this bit 24 ITRG Interval Timer as trigger for Multiple Channel Read RAN 0 1 Enable Interval Timer as trigger for multiple channel read 0 Disable Interval Timer as trigger for multiple channel read 23 SL5 Enable Multiple Channel Read for the corresponding R W 0 2 Iti ch read enables multi channel rea 21 0 disables multi channel read 20 SL2 See chapter 6 4 Multiple Channel Read for details 19 SL1 18 SL0 17 PRL5 Manual Counter Preload W 0 16 PRL4 Writing a 1 issues a preload of the corresponding 15 PRL counter with the value of the Counter Preload Register 3 This preload method is only possible for channels in a 14 PRL2 None Reference Mode 13 PRL1 Before using this preload method the corresponding 12 PRLO Preload Registers must be loaded with valid 11 10 165 1 0 Interface Control R W 0 9 8 IC4 1 0 IC Mode 7 6 IC3 1 0 00 Channel disabled 5 4 IC2 1 0 01 SSI Mode 3 2 1 0 10 Counter Mode 1 0 ICO 1 0 11 Channel disabled the selection between normal SSI
27. RUPT STATUS REGISTER TEST REGISTER PCI9030 HEADER PCI9030 PCI BASE ADDRESS USAGE PCI9030 LOCAL CONFIGURATION REGISTER CONFIGURATION EEPROM TPMC117 LOCAL BUS LITTLE BIG ENDIAN SSI STANDARD MODE SELECTION SSI LISTEN ONLY MODE SELECTION SSI LISTEN ONLY SETUP MODE BEHAVIOR DIFFERENCES INPUT MODES CLOCK PRESCALER COUNT DIRECTIONS INDEX CONTROL MODE EVENTS INDEX CONTROL MODE INTERRUPT GENERATION MULTIPLE CHANNEL READ DATA AVAILABILITY INTERVAL TIMER CLOCK PERIODS DIP SWITCH SIGNAL ASSIGNMENT DIP SWITCH SETTINGS DIGITAL INPUT CHARACTERISTICS PIN ASSIGNMENT FRONT CONNECTOR PIN ASSIGNMENT FRONT I O CONNECTOR TEWS gt TECHNOLOGIES Page 7 of 52 TEWS gt TECHNOLOGIES 1 Product Description The TPMC117 is a standard single width 32 bit PMC module and offers six independent channels Each of these channels can operate as a standard SSI interface controller in a SSI Listen only Mode as an incremental encoder or general purpose counter The standard SSI interface controller outputs a clock burst to the absolute encoder and receives the returned positional data The SSI interface controller operates with a programmable clock rate from ius to 15 and programmable data word length from 1 bit to 32 bit In Listen only Mode the channel listens to an existing SSI interface to observe its data transfer It takes both the SSI clock and data as inputs In Listen only Mode the channel also has a programmabl
28. annaaien a a doc ma gate Ca ae aaO uaa 32 5 CONFIGURATION HINTS I u 33 5 1 Big C 33 6 FUNCTIONAL DESCRIPTION 228 uud cava Av dau 35 61 SSI Short DeSCHIPti OM MP L 35 6 2 SSIM6d6 22 u u esate bev ee qas asas 36 6 2 1 Standard SSI Interface Controller 36 6 2 2 SSI Listen Only 37 6 2 3 SSI Mode behavior differences 38 etidm 39 EC Neap E M 39 0 3 1 1 Timer cL 39 6 3 1 2 Direction Count Aun EEEN ERA UREAN 39 6 3 1 3 Up Down Cou 39 6 3 1 4 Quadrature 40 6 3 2 Special Count 40 6 3 2 1 Divide Dy N u aaa uka 40 6322 Single Cycle nnd ex hada RP aaa 40 117 User Manual Issue 1 0 4 Page 4 of 52 TEWS gt TECHNOLOGIES 6 3 3 Index Control Mo9geSu u uuu ette EE Eva EPOR a EBORE PY EDD Fede 41 6 3 3 1 No iiesiassiecatacccdeanasavavsiavacnessanateestacevdeanasavaesdanavanasaadVavataravanandaavatsbavavatabaawaevaaaied 41 63 3 2 Load
29. ata transfer is initiated by the observed SSI interface The positional data will be received and processed parity check gray to binary code conversion and the end of the data transfer is indicated with the deassertion of the Busy bit If enabled an interrupt is asserted and the positional data can be read in the Data Register Reading the Data Register will set the Busy bit to 1 and the channel is listening again Note that in this mode the clock rate setting in the Control Register is ignored the Clock Rate will be detected automatically Writes to the Data Register are also ignored for channels in this mode In case of a partial transmission a read error will be issued in the Status Register To detect read errors the width of the first SSI clock pulse is measured to detect the clock rate This clock rate is multiplied by 4 and used as the initial value for a watchdog timer Every new received bit resets the watchdog timer until either the programmed data word length is reached successful read or a timeout occurs read error In case of a timeout the Read Error bit is set to 1 Depending on the BREAK setting in the Control Register the channel ignores a read error and continues listening or it stops to listen Reasons for a read error are e The number of data bits set in the control register does not match the actual size of the received transmission e Only a partial transmission was monitored this could happen w
30. ble SSI channels need time for the conversion to complete To indicate that all data is available the MCRST bit in the Global Control Register will be set to 1 This bit will stay 1 until the Data Registers of all enabled channels were read Then it changes back to 0 To reset a Multiple Channel Read sequence beforehand write 1 to the MCRST bit SSI Counter SSI amp Counter Data availability When all channel Instantly SSI When all conversions are channel conversions complete are completed Counter Instantly Data availability MCRST 1 MCRST 1 MCRST 1 indication Counter data may already be read before MCRST 1 Table 6 12 Multiple Channel Read data availability Example Channels 1 3 are configured for SSI mode channels 4 6 are configured for counter mode Channels 1 4 and 6 are enabled for Multiple Channel Read A write to the MCRTR bit starts the Multiple Channel Read Channel 1 starts a conversion and the data of channels 4 and 6 are latched The data of the enabled counter channels is instantly available and can be read at once The SSI data is not available until MCRST is set to 1 When all enabled channels were read MCRST is reset to 0 TPMC117 User Manual Issue 1 0 4 Page 44 of 52 TEWS gt TECHNOLOGIES There is no designated interrupt to indicate the completion of a Multiple Channel Read Alternatively an interrupt can be set up for
31. cess Reset Value 31 25 Reserved always reads as 0 0 24 TSTEN Enable Test Output R W 0 1 Test Output enabled 0 Test Output disabled 23 CLK5 SSI Clock outputs R W 0 22 CLK4 When is 1 these bits will control the SSI clock 21 CLK3 outputs 20 CLK2 19 CLK1 18 CLKO 17 15 Channel 6 Inputs R 0 16 B5 15 A5 14 14 Channel 4 Inputs R 0 13 B4 12 A4 11 Channel 3 Inputs R 0 10 B3 9 A3 8 2 Channel 2 Inputs R 0 7 B2 6 A2 5 I Channel 1 Inputs R 0 4 B1 3 A1 2 10 Channel 0 Inputs R 0 1 BO 0 AO Table 3 16 Test Register TPMC117 User Manual Issue 1 0 4 Page 27 of 52 4 PCI9030 Target Chip 4 1 PCI Configuration Registers PCR 4 1 1 PCI9030 Header TEWS gt TECHNOLOGIES PCI CFG Write 0 to all unused Reserved bits PCI Initial Values Register writeable Hex Values Address 31 24 23 16 15 8 7 0 0x00 Device ID Vendor ID N 0075 1498 0x04 Status Command Y 0280 0000 0x08 Class Code Revision ID N 118000 00 0x0C BIST Header Type PCI Latency Cache Line Y 7 0 00 00 00 00 Timer Size 0x10 Base Address 0 for MEM Mapped Config Registers Y FFFFFF80 0x14 PCI Base Address 1 for I O Mapped Config Registers Y FFFFFF81 0x18 PCI Base Address 2 for Local Address Space 0 Y 0x1C PCI Base Address 3 for Local Address Space 1 Y 00000000 0x20 PCI Base Address 4 for Local A
32. ddress Space 2 Y 00000000 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 0x28 Card bus Information Structure Pointer N 00000000 0x2C Subsystem ID Subsystem Vendor ID N 000A 1498 0x30 PCI Base Address for Local Expansion ROM Y 00000000 0x34 Reserved New Cap Ptr N 000000 40 0x38 Reserved N 00000000 0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y 7 0 00 00 01 00 0x40 PM Cap PM Nxt Cap PM Cap ID N 4801 48 01 0x44 PM Data PM CSR EXT CSR Y 00 00 0000 0x48 Reserved HS CSR HS Nxt Cap HS Cap ID 23 16 00 00 4C 06 0x4C VPD Address VPD Nxt Cap VPD ID Y 31 16 0000 00 03 0x50 VPD Data Y 00000000 Table 4 1 PCI9030 Header TPMC117 User Manual Issue 1 0 4 Page 28 of 52 TEWS gt TECHNOLOGIES 4 1 2 PCI Base Address Initialization PCI Base Address Initialization is scope of the PCI host software 9030 PCI Base Address Initialization 1 Write OxFFFF_FFFF to the PCI9030 PCI Base Address Register 2 Read back the PCI9030 PCI Base Address Register 3 For PCI Base Address Registers 0 5 check bit 0 for PCI Address Space Bit 0 0 requires PCI Memory Space mapping Bit 0 1 requires PCI I O Space mapping For the PCI Expansion ROM Base Address Register check bit 0 for usage Bit 0 0 Expansion ROM not used Bit 0 1 Expansion ROM used 4 For PCI I O Space mapping starting at bit location 2 the first bit set determines the size of the required PCI I O Space size
33. ded TTL input leave the inverting input A open and connect the TTL signal to the noninverting input A The1200 termination resistor must be switched off when using single ended TTL input signals Voc Figure 7 3 Single ended Input Wiring The switching point lies at approx 1 6V with a hysteresis of about 0 4 mV TPMC117 User Manual Issue 1 0 4 Page 47 of 52 TEWS gt TECHNOLOGIES 7 1 3 Differential 9422 The following schematic shows the principle input wiring for one differential RS422 encoder signal RS422 input signals should be terminated The encoder input is fail safe based so that unused inputs can be left open Voc Vcc Figure 7 4 Differential Input Wiring It is recommended to terminate differential RS422 input signals 7 2 Clock Output Wiring The TPMC117 adheres to the original SSI specification that featured galvanic insulation with optocouplers Therefore the clock inputs in the sensor did not need a ground reference Nowadays the sensor s clock inputs are often build with conventional RS422 receivers which do need a ground reference The TPMC117 s clock drivers are referenced to circuit ground which is not available at the connector In this case the clock s ground reference must be connected to the system ground which must be available somewhere in the chassis TPMC117 Absolute Encoder Figure 7 5 Clock Output Wiring with Optocoupler Input TPMC117 User Manual Issue 1
34. e Byte Width Mode Space Offset in PCI Mapping Bit Configuration Space 0 2 0x18 MEM 256 32 BIG Local Register Address Space 1 3 0x1C Not Used 2 4 0x20 Not Used 3 5 0x24 Not Used Table 3 1 PCI9030 Local Space Configuration TPMC117 User Manual Issue 1 0 4 Page 11 of 52 TEWS amp 3 2 Local Register Address Space PCI Base Address PCI9030 PCI Base Address 2 Offset 0x18 in PCI Configuration Space Offset to PCI Register Name Size Base Address 2 Bit 0x00 Control Register 0 32 0x04 Data Register 0 32 0x08 Status Register 0 32 0x0C Counter Preload Register 0 32 0x10 Counter Compare Register 0 32 0x14 Counter Command Register 0 32 0x18 Control Register 1 32 0x1C Data Register 1 32 0x20 Status Register 1 32 0x24 Counter Preload Register 1 32 0x28 Counter Compare Register 1 32 0 2 Counter Command Register 1 32 0x30 Control Register 2 32 0x34 Data Register 2 32 0x38 Status Register 2 32 Ox3C Counter Preload Register 2 32 0x40 Counter Compare Register 2 32 0x44 Counter Command Register 2 32 0x48 Control Register 3 32 0x4C Data Register 3 32 0x50 Status Register 3 32 0x54 Counter Preload Register 3 32 0x58 Counter Compare Register 3 32 0x5C Counter Command Register 3 32 0x60 Control Register 4 32 0x64 Data Register 4 32 0x68 Status Register 4 32 0x6C Counter Preload R
35. e 46 7 1 2 Single Ended TTL 47 7 1 3 Differential R8422 eeesseseseeeeeee nee nn 48 7 2 Clock OUTPUT mee 48 7 3 Digital Input CharacteristiGs reri 49 8 PIN ASSIGNMENT 1 0 CONNECTOR 50 8 1 Front Panel 1 0 Connector u u u u u u u u U uuu ssssuwassuwswwassuusquqskusawuqasuwsuuwa 50 8 2 P14 Back I O Connectolr U 52 TPMC117 User Manual Issue 1 0 4 Page 5 of 52 FIGURE 1 1 FIGURE 6 1 FIGURE 6 2 FIGURE 6 3 FIGURE 6 4 FIGURE 6 5 FIGURE 7 1 FIGURE 7 2 FIGURE 7 3 FIGURE 7 4 FIGURE 7 5 FIGURE 7 6 FIGURE 7 7 FIGURE 8 1 TPMC117 User Manual Issue 1 0 4 TEWS gt TECHNOLOGIES List of Figures 0 8 SSI TIMING EXAMPLE etudiant ttt icti iaae 35 WIRING EXAMPLE CHANNEL 0 SSI INTERFACE CONTROLLER MODE 36 WIRING EXAMPLE CHANNEL 0 LISTEN ONLY MODE eee 37 QUADRATURE SIGNALS riter iine uaa depu 40 REFERENCE MODE PRELOAD 43 INPUT WIRING 46 TER
36. e Interrupt disabled An interrupt will be generated on a control mode event 14 CIEN2 13 CIEN1 12 CIENO 11 5 Enable Match Interrupt R W 0 10 4 1 Counter Match Interrupt enabled 9 MIEN3 0 Counter Match Interrupt disabled An interrupt will be generated when the counter value 8 MIEN2 matches the Counter Compare Register 7 MIEN1 6 MIENO TPMC117 User Manual Issue 1 0 4 Page 24 of 52 TEWS 2 TECHNOLOGIES Table 3 14 Interrupt Enable Register 3 15 Interrupt Status Register The interrupt status is updated only if the interrupt enable bit of the corresponding channel is set to 1 Otherwise the interrupt status is read as 0 Bit Symbol Description Access Reset Value 5 SIEN5 Enable SSI Interrupt R W 0 4 SIEN4 1 SSI Data Valid Interrupt enabled 3 SIEN3 0 SSI Data Valid Interrupt disabled An interrupt will be generated when a SSI transmission 2 SIEN2 completes and the Busy status bit is set to 0 1 SIEN1 0 SIENO Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved Digital Input IRQ Status Control lt LO N T LO mE lol ol ol o o 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 Mode IRQ Status Match IRQ Sta
37. e counter acts as quadrature counter A input is quadrature input A B input is quadrature input B The quadrature inputs can be interpreted as 1x 2x or 4x counting 1x lets the counter count once for each full cycle of the quadrature inputs 2x lets the counter count once for each half cycle of the quadrature inputs and 4x lets the counter count once for each quarter cycle of the quadrature inputs The count direction increase or decrease is determined by the relative phase of the A and B signals The maximum input frequency is 2 MHz In 4x mode the counter counts with max 8 MHz Signal A p wx Signal B iT i 1x single 2x douple peret Tg 4x quad Figure 6 4 Quadrature Signals 6 3 2 Special Count Modes In normal operation the counter is a cycling counter Two additional special count modes are available The Count Modes are available for every Input Mode 6 3 2 1 Divide by N The counter is enabled in the Control Register and will run until it is disabled The counter is loaded with the content of the preload register every time the counter creates a borrow or a carry 6 3 2 2 Single Cycle The counter is enabled in the Control Register and will start on following events e A manual preload or reset in the Counter Command Register e A manual counter preload in the Global Control Register e A control mode event in
38. e data word length from 1 bit to 32 bit the SSI clock rate of the observed SSI interface can be in the range of 1 5 to 15us In both modes the data word can be encoded in Binary or in Gray code and with odd even or no parity The 32 bit incremental encoder counter is a preloadable up and down counter The counter is programmable for single double and quadruple analysis of the encoder signals In conjunction with the isolated 24V digital inputs it provides the possibility of automatic preload of the counter whenever the motion system passes a reference position The 32 bit general purpose preloadable up and down counter can be fed with an internal clock or with external signals Both counter modes offer a 32 bit preload register a 32 bit compare register and various count modes 3 isolated inputs SSI data amp counter modes 1 isolated 24V digital input 1 SSI clock output Figure 1 1 Block Diagram A Multiple Channel Read function latches the actual values of all enabled channels whose values can then be read without interfering with normal function In addition the TPMC117 provides a 16 bit down counter with preload register which allows timing intervals of up to 65ms It can be used as reference timer for closed loop applications or as trigger for the Multiple Channel Read function All data inputs are isolated The level of the input signals can be RS422 or TTL The input signals pass a digital filter for noise su
39. egister 4 32 0x70 Counter Compare Register 4 32 0x74 Counter Command Register 4 32 TPMC117 User Manual Issue 1 0 4 Page 12 of 52 TEWS gt TECHNOLOGIES Offset to PCI Register Name Size Base Address 2 Bit 0x78 Control Register 5 32 0x7C Data Register 5 32 0x80 Status Register 5 32 0x84 Counter Preload Register 5 32 0x88 Counter Compare Register 5 32 0x8C Counter Command Register 5 32 0x90 Digital Input Register 32 0x94 Interval Timer Control Register 32 0x98 Interval Timer Preload Register 32 0 9 Interval Timer Data Register 32 Global Control Register 32 4 Interrupt Enable Register 32 8 Interrupt Status Register 32 OxAC Test Register 32 Table 3 2 Local Register Address Space 3 3 Control Register The Control Register is divided into two parts bits 15 0 are dedicated for SSI control bits 31 16 are dedicated for Counter control Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Counter Setup 1 0 POL ICM SCM CLKDIV INPUT Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BREAK MODE SSI Setup BC CODE ZB EO PAR CR TPMC117 User Manual Issue 1 0 4 Page 13 of 52 TEWS 2 TECHNOLOGIES Bit Symbol Description Access Reset Value 31 29 Reserved always reads as 0 0 28 26 POL A B I Polarity RAN 000 2 0 The Input Polarity Control can be used to adapt the input to the input source
40. hen the mode is switched and a transmission is in progress on the observed SSI interface In the case that a SSI communication is in progress when the mode is switched to Listen only a read error will be issued for the first reading 6 2 3 SSI Mode behavior differences Control Register Standard SSI Interface Mode Control Register SSI bits fully used Bit 14 MODE is set to 0 Listen only Mode Clock rate setting in Control Register is don t care Bit 14 MODE is set to 1 Status Register Read Error Bit Busy bit 1 during transmission Read Error bit is always 0 Busy bit 1 during transmission or after the data word was read channel is listening again Read Error bit is set 1 erroneous transmission Connections Connect external SSI data outputs to TPMC117 DATA inputs Connect external SSI Clock inputs to TPMC117 CLK OUT outputs Connect external SSI data to TPMC117 DATA inputs Connect external SSI clock to TPMC117 CLK IN inputs Data Transfer Start Data transfer is initiated by a write to the Data Register or a Multiple Channel Read Data transfer is initiated by external SSI interface controller Table 6 5 Mode behavior differences TPMC117 User Manual Issue 1 0 4 Page 38 of 52 TEWS gt TECHNOLOGIES 6 3 Counter Mode The TPMC1 17 counter offers 4 input modes 2 special cou
41. ir respective owners Page 2 of 52 TEWS gt TECHNOLOGIES Issue Description Date Preliminary Issue December 2005 1 0 First Issue September 2006 1 0 1 New notation for HW Engineering Documentation Releases February 2009 1 0 2 Added 7 2 Clock Output Wiring June 2010 1 0 3 Added 20 Variant July 2012 1 0 4 General Revision August 2014 TPMC117 User Manual Issue 1 0 4 Page 3 of 52 TEWS gt TECHNOLOGIES Table of Contents 1 PRODUCT DESCRIPTION 8 2 TECHNICAL SPECIFICATION U 10 3 LOCAL SPACE ADDRESSING J U u u U u u u u Qu 11 3 1 PCI9030 Local Space Configuration U U uu u u u 11 3 2 Local Register Address Space 12 3 3 Control HeglsSter Yu Ree 13 34 Datta RBe gIS IF lll lll lasta 16 3 4 1 Data Register SSI Mode 16 3 4 2 Data Register in Counter 16 3 5 Sua 17 3 6 Counter Preload Register U 19 3 7 Counter Compare Register J U u u u u
42. itored in the Control Register After successful execution the mode is reset from Index Mode to No I Control Mode TPMC117 User Manual Issue 1 0 4 Page 43 of 52 TEWS gt TECHNOLOGIES 6 3 4 Data Register Lock The Data Register is loaded and locked with the actual counter value on following conditions e Latch in Mode e Multiple channel read The Data Register is locked until following conditions are met e Aread access to the Data Register e A write 1 to the RONT bit in the Counter Command Register Until the lock is released the Data Register will not load again The status of the Data Register lock can be monitored in the Status Register DRL When the lock is released the Data Register retains its value until it is loaded again When a Multiple channel read is issued or a Latch Mode event occurs while a Data Register is locked the Data Register content will be retained and the Data Register Lock Overflow OVFL will be set to indicate that data was lost 6 4 Multiple Channel Read The Multiple Channel Read option is enabled in the Global Control Register A Multiple Channel Read is triggered by writing 1 to the MCRTR bit Alternatively the interval timer can be used to trigger a multiple channel read For Counter mode the Multiple Channel Read latches the enabled counter channels For SSI mode the Multiple Channel Read starts a conversion for the enabled SSI channels The data of counter channels is instantly availa
43. mode and SSI listen only mode is done the Channel Control Register Table 3 13 Global Control Register TPMC117 User Manual Issue 1 0 4 Page 23 of 52 3 14 Interrupt Enable Register For pending interrupts and interrupt acknowledge see the Interrupt Status Register TEWS gt TECHNOLOGIES Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved Enable Digital Input IRQ Enable 2 z zs 0 E i imi ii Hi Di ju os Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Control Mode IRQ Enable Match IRQ Enable SSI IRQ e N T LO N LO co e T 2 2 2 2 Z W Lj LL lH LI iH HJ iH LH LI DH TH Li JO 2 gt gt gt gt gt C Bit Symbol Description Access Reset Value 31 25 Reserved always reads as 0 0 24 TIEN Interval Timer Interrupt R W 0 23 DIEN5 Enable 24V digital input Interrupt R W 0 22 DIEN4 1 Digital Input Interrupt enabled 21 DIEN3 0 Digital Input Interrupt disabled u An interrupt will be generated on an rising or falling edge 20 DIEM of the digital input 19 DIEN1 18 DIENO 17 CIEN5 Enable Control Mode Interrupt R W 0 16 4 1 Control Mode Interrupt enabled 15 CIEN3 0 Control Mad
44. nel is listening again The data register may not contain valid data if the serial data transfer is in progress the corresponding Busy bit is read as 1 3 4 2 Data Register in Counter Mode The Data Register contains the actual counter value While a Multiple Channel Read is in progress this register may contain latched data In Latch on l control mode this register contains latched data after a control mode event See chapter Data Register Lock for details TPMC117 User Manual Issue 1 0 4 Page 16 of 52 3 5 Status Register The Status Register is divided into two parts bits 15 0 are dedicated for SSI status bits 31 16 are dedicated for Counter status TEWS gt TECHNOLOGIES Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Counter Status 18 2 5 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 SSI Status m Bit Symbol Description Access Reset Value 31 24 Reserved always reads as 40 0 23 SGL Single Cycle active R 0 In Single Cycle counting mode this bit is set to 1 when the counter is active It is reset to 0 when the counter has counted down to zero 22 OVFL Data Register Latch Overflow R C 0 When a Latch Mode event occurs while the Data Register L
45. next index pulse after entering the area with reference input active triggers the preload function for the counter TPMC117 User Manual Issue 1 0 4 Page 42 of 52 TEWS gt TECHNOLOGIES Position 1b Direction is backwards and the reference input is inactive The host software must move further backwards and after entering the area with reference input active the next index pulse triggers the preload function for the counter Encoder Motion Area Forward Reference Switching Point Backwards Reference Switch Active Inactive Index Signal Counter Preload 80 81 1 50 52 lt lt Q 50 52 51 tb Figure 6 5 Reference mode preload example A correct execution of the reference function can be monitored in the Control Register After successful execution the mode is reset from Reference Mode to No I Control Mode 6 3 3 7 Auto Reference Mode This mode is the automation of the Reference Mode Every time the reference switching point and a following index pulse are crossed during backward direction a new preload is generated In Auto Reference Mode there is no change of the Index Control Mode in the Control Register 6 3 3 8 Index Mode In this mode the reference input is not used Only the index impulse produces a counter preload After setting this mode the next occurrence of the index signal independent from direction will preload the counter A correct execution of this preload function can be mon
46. nfiguration Registers are loaded from the on board serial configuration EEPROM The PCI base address for the PCI9030 Local Configuration Registers is PCI9030 PCI Base Address 0 PCI Memory Space Offset 0x10 in the PCI9030 PCI Configuration Register Space or PCI9030 PCI Base Address 1 PCI I O Space Offset 0x14 in the PCI9030 PCI Configuration Register Space Do not change hardware dependent bit settings in the 9030 Local Configuration Registers Offset from Register Value Description PCI Base Address 0x00 Local Address Space 0 Range OxOFFF 256 Bytes Memory Space 0x04 Local Address Space 1 Range 0x0000_0000 Not used 0x08 Local Address Space 2 Range 0x0000_0000 Not used 0x0C Local Address Space 3 Range 0x0000_0000 Not used 0x10 Local Exp ROM Range 0x0000_0000 Not used 0x14 Local Re map Register Space 0 0x0000_0001 Enabled Base Address 0x0000 0x18 Local Re map Register Space 1 0x0000_0000 Not used 0x1C Local Re map Register Space 2 0x0000_0000 Not used 0x20 Local Re map Register Space 3 0x0000_0000 Not used 0x24 Local Re map Register ROM 0x0000_0000 Not used 0x28 Local Address Space 0 Descriptor 0x4180_0020 Local Space 0 Configuration 0x2C Local Address Space 1 Descriptor 0x0000_0000 Not used 0x30 Local Address Space 2 Descriptor 0x0000_0000 Not used 0x34 Local Address Space 3 Descriptor 0x0000_0000 Not used 0x38 Local Exp ROM Descriptor 0x0000_00
47. nt modes and 8 index control modes 6 3 1 Input Modes The input mode determines how the counter interprets the A and B input lines Input Mode A Input B Input I Input Timer not used not used Direction Count Count Count direction up down Available for Input Up Down Count Count UP Count DOWN Control Modes Quadrature Count Quadrature A Quadrature B Table 6 6 Input Modes Changing the input mode does not affect the counter reading If no input mode is selected the counter is disabled 6 3 1 1 Timer Mode In Timer mode the counter uses an internal clock prescaler as input Bits Prescaler Clock frequency 00 1x 32 MHz 01 2x 16 MHz 10 4x 8 MHz 11 8x 4 MHz Table 6 7 Clock Prescaler 6 3 1 2 Direction Count The counter acts as up down counter Counting pulses are generated when a transition from low to high of the A input is detected The B input determines the count direction B input Count Direction 0 Down 1 Up Table 6 8 Count Directions 6 3 1 3 Up Down Count The counter acts as up down counter Counting pulses are generated when a transition from low to high of either the A or the B input is detected The A input counts up the B input counts down Simultaneous transitions on the A and B input do not generate a counting pulse TPMC117 User Manual Issue 1 0 4 Page 39 of 52 TEWS gt TECHNOLOGIES 6 3 1 4 Quadrature Count Th
48. ock is still active the data in the Data Register will be retained and this bit will be set to indicate that data was lost This bit must be reset by writing a 1 to this bit 21 DRL Data Register Latch R C 0 This bit is set to 1 when the Data Register is locked due to a Latch on l or a Multiple Channel Read This bit is cleared after a read access to the Data Register or by writing a 1 to this bit 20 DIR Count Direction R 0 This bit indicates the counting direction of the counter 1 indicates up indicates down In the Up Down Count mode this bit indicates the direction at the last count In the Direction Count mode this bit corresponds to the l input 19 SGN Sign R 0 The Sign bit is set to 1 when the counter overflows and is set to 0 when the counter underflows After reset or power up this bit should be considered as don t care until the first Carry or Borrow occurred TPMC117 User Manual Issue 1 0 4 Page 17 of 52 TEWS 2 TECHNOLOGIES Bit Symbol Description Access Reset Value MAT Match This bit is set to 1 when the counter value matches the value of the Counter Compare Register This bit must be reset by writing a 1 to this bit R C 0 CRY Carry This bit is set to 1 when the counter changes from OxFFFFFFFF to 0x00000000 This bit must be reset by writing a 1 to this bit R C BOR Borrow This bit is set to 1 when
49. ppression before they are further used The level of the SSI clock output signals is RS422 TPMC117 User Manual Issue 1 0 4 Page 8 of 52 TEWS E TECHNOLOGIES Each of the six motion control channels of the TPMC117 offers one isolated 24V digital input The input circuit ensures a defined switching point and polarization protection against confusing the pole The input has an electronic debounce circuit All six 24V digital inputs can generate an interrupt triggered on rising or falling edge Depending on the selected mode the input can be used as general purpose input or reference input All TPMC117 10R signals are accessible through a HD68 SCSI 3 type front I O connector The TPMC117 20R offers P14 back I O and a dummy front panel The TPMC1 17 can operate with 3 3V and 5 0V PCI I O signaling voltage TPMC117 User Manual Issue 1 0 4 Page 9 of 52 TEWS gt TECHNOLOGIES 2 Technical Specification PMC Interface Mechanical Interface PCI Mezzanine Card PMC Interface Single Size Electrical Interface PCI Rev 2 2 compliant 33 MHz 32 bit PCI 3 3V and 5V PCI Signaling Voltage On Board Devices PCI Target Chip Interface PCI9030 PLX Technology Number of Channels 6 isolated channels with 3 input lines and 1 output line per channel Input Levels RS422 differential and TTL single ended ESD Protection 15kV Human Body Model 8kV IEC 1000 4 2 Contact Discharge 15kV IEC 1
50. sy input signals the A B and l inputs are digitally filtered A change in the input level is only detected when the input line is stable for at least 100ns TPMC117 User Manual Issue 1 0 4 Page 45 of 52 TEWS amp TECHNOLOGIES 7 Hardware Interface 7 1 Encoder Counter Input Wiring The following schematic shows the principle input wiring for one encoder signal Vec Vcc Figure 7 1 Input Wiring The 1200 termination resistor is switchable via DIP switches For single ended TTL signals the switch must be left open default for differential RS422 signals the switch should be closed T 1 1 Termination Resistor DIP Switches The termination DIP switches are located near the I O connector refer to the following figure PCI9030 r 1 Figure 7 2 Termination Resistor DIP Switches TPMC117 User Manual Issue 1 0 4 Page 46 of 52 TEWS gt TECHNOLOGIES Each channel has a dedicated DIP switch for its input signals Switch Signal 1 ENC A 2 ENC B 3 4 not used Table 7 1 DIP Switch Signal Assignment Switch Setting Termination ON Enabled OFF Disabled Table 7 2 DIP Switch Settings The Factory setting of the DIP switch is OFF hence the input configuration is single ended TTL 7 1 2 Single Ended TTL The following schematic shows the principle input wiring for one single ended TTL encoder signal For single en
51. ta word was read Table 3 5 SSI Status Register TPMC117 User Manual Issue 1 0 4 Page 18 of 52 TEWS gt TECHNOLOGIES 3 6 Counter Preload Register Bit Symbol Description Access Reset Value 31 0 Counter Preload Register RAN 0 The value of this register can be loaded into the counter by Setting bit 1 LCNT of the Counter Command Register An impulse on the l input when the Load on l mode is active Automatically in the Divide by N mode every time the counter creates a borrow or a carry Reference modes Table 3 6 Counter Preload Register 3 7 Counter Compare Register Bit Symbol Description Access Reset Value 31 0 Counter Compare Register R W 1 Every time the counter matches the Counter Compare Register value bit 18 MAT of the Status Register is set to 1 and if enabled an interrupt is generated Table 3 7 Counter Compare Register 3 8 Counter Command Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved Bit 15 14 13 12 11 40 9 8 7 6 5 4 3 2 1 0 Reserved o o o o o ojo o o ol o o o o 117 User Manual Issue 1 0 4 Page 19 of 52 TEWS 2 TECHNOLOGIES
52. the counter changes from 0x00000000 to OxFFFFFFFF This bit must be reset by writing a 1 to this bit R C 15 3 RER Reserved always reads as 40 Read Error 1 Data is invalid because of an error during the last transmission 0 Data OK This bit is only valid for channels in Listen only mode For channels in Standard 551 Interface Controller mode this bit will always read 0 Reasons for a read error are The number of data bits set in the control register does not match the actual size of the received transmission Only a partial transmission was received this could happen when the mode is switched and a transmission is in progress on the observed SSl interface PRY Parity Error 1 Parity Error at the last data transmission 0 No Parity Error at the last data transmission During a transmission the parity error bit is not valid The parity error status is updated only if the parity enable bit of the corresponding channel is set to 1 Otherwise the parity status is read as 0 BSY Busy Bit 0 Data Ready set after every completed transmission even if a parity or a read error was issued In Standard SSI Interface Controller mode Busy Bit 1 indicates a transmission in progress In Listen only Mode the Busy Bit is set to 1 when a transmission is in progress It is set to 0 when transmission was received and stays until the da
53. tus SSI IRQ Status e T LO st N LO N lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt E E o 5 6 o 69 9 b b b b 5 5 OJO gt gt gt gt gt gt O o Bit Symbol Description Access Reset Value 31 25 Reserved always reads as 0 0 24 TISTA Pending Interval Timer Interrupts Read R C 0 Interrupt acknowledge Write On a read access this bit indicates a pending Interval Timer interrupt A 1 indicates a pending interrupt The interrupt is acknowledged by writing a 1 to this bit 23 DISTA5 Pending Digital Input Interrupts Read R C 0 22 DISTA4 Interrupt acknowledge Write 24 DISTA3 On a read access these bits indicate the channels with pending digital input interrupts 1 indicates a pending 20 DISTA2 interrupt 19 DISTA1 The interrupts are acknowledged by writing a 1 to the 18 DISTAO according bit TPMC117 User Manual Issue 1 0 4 Page 25 of 52 TEWS 2 TECHNOLOGIES Bit Symbol Description Access Reset Value 17 CISTA5 Pending Control Mode Interrupts Read R C 0 16 CISTA4 Interrupt acknowledge Write 15 CISTA3 On a read access these bits indicate the channels with pending control mode interrupts A 1 indicates a pending 14 CISTA2 interrupt 13 CISTA1
54. ue of 0 indicates Little Endian Use the PCI Base Address 0 Offset or PCI Base Address 1 Offset Short cut Offset LASOBRD LAS1BRD LAS2BRD LAS3BRD EROMBRD Name 0x28 0 2 0 30 0x34 0x38 Local Address Space 0 Bus Region Description Register Local Address Space 1 Bus Region Description Register Local Address Space 2 Bus Region Description Register Local Address Space 3 Bus Region Description Register Expansion ROM Bus Region Description Register You could also use the PCI Base Address 1 I O Mapped Configuration Registers TPMC117 User Manual Issue 1 0 4 Page 34 of 52 TEWS gt TECHNOLOGIES 6 Functional Description Each channel can either work as a SSI interface or as an encoder general purpose counter The choice between both modes is made in the Global Control Register on a per channel base In addition to this main functionality the TPMC117 offers one isolated 24V digital input per channel plus an interval timer 6 1 SSI Short Description The Synchronous Serial Interface SSI is based on two differential signal lines CLOCK and DATA The CLOCK line is an input the DATA line is an output of the absolute encoder Pr UN CLOCK tm DATA MSB MSB 1 MSB 2 x LSB 1 LSB Parity Dn 1 Dn 2 D1 Zero Bit Parity Bit opt opt T Clock Period n Number of Data Bits tm Recovery Time Figure 6
55. ut Source 000 Counter disabled 001 Timer Mode Up Internal Clock Prescaler 010 Timer Mode Down Internal Clock Prescaler 011 Direction Count Input A amp Input B 100 Up Down Count Input A amp Input B 101 Quadrature Count 1x Input A amp Input B 110 Quadrature Count 2x Input A amp Input B 111 Quadrature Count 4 Input A amp Input B See chapter 6 3 1 Input Modes for details 15 BREAK Break on Read Error Listen only R W 0 1 The channel stops to listen on read errors 0 Read errors are ignored and the channel resumes to listen 14 MODE 4 SSI Listen only Mode R W 0 0 Standard 551 Interface Controller 13 5 Number of Data Bits R W 0 42 BC4 Bits are used to program the number of bits of the serial 11 BC absolute encoder It can be read and written by software 3 The data bits must be programmed in the range from 1 to 32 10 BC2 5 0x01 to 0x20 means 1 to 32 bit 9 BC1 5 0x00 not valid 8 BC5 BCO 0x21 to not valid 7 CODE SSI Data word coding R W 0 1 Gray Code The data word is converted into binary code 0 Binary Code 6 ZB Parity Bit with Zero Bit controls the clock cycles R W 0 1 two additional clock cycles 0 one additional clock cycle are provided to get the parity bit 5 EO Controls the parity detection R W 0 1 odd parity 0 even parity This bit is ignored if bit 4 is set to

TPMC117 - TEWS TECHNOLOGIES

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