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SLLIMM™-nano small low-loss intelligent molded module

1. Reg AV oe Alo 3 Vem V Both forward characteristics are temperature dependent and so must be considered under a specified temperature The linear approximations can be translated for IGBT in the following equation Equation 15 Veelic Vro Rce ic and for freewheeling diode Equation 16 Vim lfm Fo Rak ifm The conduction losses of IGBT and diode can be derived as the time integral of the product of conduction current and voltage across the devices as follows Equation 17 e if Peond_IGBT Vee Ip t dt Vro Ig t Reoe O Jat Equation 18 P PAL a iat 2 Veo ik t R i t dt cond_Diode 7 A f f F 5 FO tf AK f where T is the fundamental period The different utilization mode of the SLLIMM nano modulation technique and working conditions make the power losses very difficult to estimate it is therefore necessary to fix some starting points lt Doc ID 022726 Rev 2 43 60 Power losses and dissipation AN4043 44 60 Assuming that 1 The application is a variable voltage variable frequency VVVF inverter based on sinusoidal PWM technique 2 The switching frequency is high and therefore the output currents are sinusoidal 3 The load is ideal inductive Under these conditions the output inverter current is given by Equation 19 1 cos 6 where is the current peak stands for wt and is the phase angle between output voltage
2. 0 cc ees 57 ROTerences cadecdaceetese tgs eed e career reagent eee encase 58 Revision history 2 0ctsedt rara rada asada cuetnne 59 Doc ID 022726 Rev 2 3 60 List of tables AN4043 List of tables Table 1 SLUMM nano NNE UD sass 2444054684044 4565 ee ned ead aa aa boa dees 9 Table 2 ic o In 12 Table 3 Control part of the STGIPNSH60 gt ia ccadccceencuew rara a 13 Table 4 Supply voltage and operation behavior 0 00 eee ee 14 Table 5 KOSY O savia oras nds aes ea eee eee eee adda eae eS 14 Table 6 Integrated pull up down resistor values 0 0 0 eee 19 Table 7 Interlocking function truth table of the STGIPNSH60A 0 00002 eee ee 20 Table 8 Interlocking function truth table of the STGIPN3H6O 0 0 0 2 eee 21 Table 9 Outline drawing of NDIP 26L package 0 cc eee ene 37 Table 10 Input and output pins ee ee eee 38 Table 11 Cauer and Foster RC thermal network elements 0 0000 e eee eens 49 Table 12 Document revision history 0 0 0 ce eee eee nas 59 AN4043 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 3
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5. Voc w Control supply pins for the built in ICs To prevent malfunction caused by noise and ripple in the supply voltage a good quality low ESR low ESL filter capacitor should be mounted close to these pins Gate drive supply ground Pin GND e Ground reference pin for the built in ICs e To avoid noise influence the main power circuit current should not be allowed to flow through this pin see Section 5 1 Layout suggestions lt Doc ID 022726 Rev 2 39 60 Package 40 60 AN4043 Signal input Pins HINy HINy HIN LINy LIN y LIN yy LING LING LING These pins control the operation of the built in IGBTs The signal logic of HINy HINy HINy LINy LINy and LIN yy pins is active high The IGBT associated with each of these pins is turned on when a sufficient logic higher than a specific threshold voltage is applied to these pins The signal logic of LINy LINy LIN yy pins is active low The IGBT associated with each of these pins is turned on when a logic voltage lower than a specific threshold voltage is applied to these pins The wiring of each input should be as short as possible to protect the SLLIMM nano against noise influence RC coupling circuits should be adopted for the prevention of input signal oscillation Suggested values are R 100Q and C 1nF Internal comparator non inverting only for the STGIPN3H60 Pin CIN The current sensing shunt resistor connected on each phase leg may be used
6. 1 E 00 1 01 1 E 02 1 E 03 time sec Doc ID 022726 Rev 2 47 60 Power losses and dissipation AN4043 48 60 More generally in the case of the device power is time dependent too The device temperature can be calculated by using the convolution integral method applied to Equation 31Equation 31 as follows Equation 32 t AT t zin P t dt 0 An alternative method very useful for the simulator tools is the transient thermal impedance model which provides a simple method to estimate the junction temperature rise under a transient condition By using the thermo electrical analogy the transient thermal impedance Zh can be transformed into an electrical equivalent RC network The number of RC sections increases the model details therefore a twelfth order model for Zi a based on the Cauer and Foster networks has been used in order to improve the accuracy of both models Figure 31 and Figure 32 show the general Cauer and Foster RC equivalent circuit used for the thermal impedance model Figure 31 Cauer RC equivalent circuit AM11819v1 AM11820v1 Temperatures inside the electrical RC network represent voltages power flows represent currents electrical resistances and capacitances represent thermal resistances and capacitances respectively The case temperature is represented with a DC voltage source and it can be interpreted as the initial junction temperature Transient thermal impedance models are derive
7. 12Equation 12 the initial charging time is Equation 13 6 2 2 10 120 IES A t 2 CHARGE 05 For safety reasons the initial charging time must be at least 8 1 ms lt Doc ID 022726 Rev 2 AN4043 3 3 1 Package Package The NDIP is a dual in line transfer mold package available in 26 lead version NDIP 26L able to meet demanding cost and size requirements of consumer appliance inverters It consists of a copper lead frame with power stage and control stage soldered on it and housed using the transfer molding process The excellent thermal properties of the copper allows good heat spread and heat transfer furthermore the thickness and the layout of the lead frames has been optimized in order to further reduce the thermal resistance The package pinout has been designed in order to maximize the distance between the high voltage and low voltage pins by placing the relevant pins on the opposite side of the package This is mainly useful to keep a safe distance between high voltage and low voltage pins and for an easy PCB layout Finally thanks to the transfer molding technology and design optimization the SLLIMM nano offers a high power density level in a very compact package while providing good thermal propriety electrical isolation and overall reliable performance Package structure Figure 23 contains the images and an internal structure illustration of the NDIP 26L package Figure 23 Images and intern
8. 5 V logic power supply through a pull up resistor Integrated operational amplifier only for the STGIPN3H60 Pins OP OP OPouT The op amp is completely uncommitted The op amp performance is optimized for advanced control technique FOC Thanks to the integrated op amp it is possible to realize a compact and efficient board layout minimizing the required BOM list Doc ID 022726 Rev 2 ky AN4043 Package Positive DC link Pin P e This is a DC link positive power supply pin of the inverter and it is internally connected to the collectors of the high side IGBTs e To suppress the surge voltage caused by the DC link wiring or PCB pattern inductance connect a smoothing filter capacitor close to the P pin Generally a 0 1 or 0 22 uF high frequency high voltage non inductive capacitor is recommended Negative DC link Pins Nu Ny Nw e These are the DC link negative power supply pins power ground of the inverter e These pins are connected to the low side IGBT emitters of each phase e The power ground of the application should be separated from the logic ground of the system and they should be reconnected at one specific point star connection Inverter power output Pins U V W e Inverter output pins for connecting to the inverter load e g motor ky Doc ID 022726 Rev 2 41 60 Power losses and dissipation AN4043 4 Power losses and dissipation The total power losses in an inverter are comprised of conduction lo
9. AM10495v1 The typical values of the integrated pull up down resistors are shown in Table 6 18 60 Doc ID 022726 Rev 2 ky AN4043 Electrical characteristics and functions Table 6 Integrated pull up down resistor values High side gate drivi Seo gate CAVINJ STGIPN3H60A Active high 500 kQ HIN y HINy HIN yy Low side gate drivi SOS gate SENN STGIPN3H6OA Active high 500 KQ LINy LINy LIN yy High side gate drivi girsiag gate ANVINJ STGIPN3H6O Active high 85 kQ HINy HINy HIN yy Low side gate driving STGIPN3H60 Active low 720 kQ CIN y LIN y LIN yy SD OD shutdown STGIPNSH6O Actvelow se 2 3 2 High voltage level shift The built in high voltage level shift allows direct connection between the low voltage control inputs and the high voltage power half bridge in any power application up to 600 V It is obtained thanks to the BCD offline technology which integrates in the same die bipolar devices low and medium voltage CMOS for analog and logic circuitry and high voltage DMOS transistors with a breakdown voltage in excess of 600 V This key feature eliminates the need for external optocouplers resulting in significant savings regarding component count and power losses Other advantages are high frequency operation and short input to output delays 2 3 3 Undervoltage lockout The SLLIMM nano supply voltage Vcc is continuously monitored by an undervoltage lockout UVLO circuitry which turns off the gate dri
10. and current The conduction power losses can be obtained as Equation 20 Vro p Rce l r Pcond_IGBT on E cos 8 po CE cos 0 d0 Eds Equation 21 Tio ies ae D a2 Veo l Raxl Poond_Diode E2 1 E cos o0 AK 1 E cos 0 oJeo 2T 2T 5 0 5 0 where is the duty cycle for this PWM technique and is given by Equation 22 _ 14 Mg cose gt 2 and ma is the PWM amplitude modulation index Finally solving Equation 20Equation 20 and Equation 21Equation 21 we have Equation 23 1 m cosd Ree I 1 m coso P Vra 4 2 SVE _ EA e gt LE cond_IGBT TO A 8 On 8 3m Equation 24 1 _mg cose Rax 12 1_ma cose P iode Veo E a 22 24 cond_Diode FO e 8 2T 8 WT Doc ID 022726 Rev 2 ky AN4043 4 2 lt Power losses and dissipation and therefore the conduction power losses of one device IGBT and diode are Equation 25 Peond Peond_IGBT Pcond_Diode Of course the total conduction losses per inverter are six times this value Switching power losses The switching loss is the power consumption during the turn on and turn off transients As already shown in Figure 26 it is given by the pulse of power dissipated during the turn on ton and turn off tos Experimentally it can be calculated by the time integral of product of the collector current and collector emitter voltage for the switching period However the dynamic performance is strictly related
11. between high side and low side IGBTs the SLLIMM nano provides both the dead time and the interlocking function The interlocking function is a logic operation which sets both the outputs to low level when the inputs are simultaneously active The dead time function is a safety time introduced by the device between the falling edge transition of one driver output and the rising edge of the other output If the rising edge set externally by the user occurs before the end of this dead time it is ignored and results as delayed until the end of the dead time Table 7 Interlocking function truth table of the STGIPN3H60A Condition nlenoesing H H L L half bridge tri state 0 age Stale L L L L half bridge tri state 1 ad SAE H i H L low side direct driving 1 3 ogle state 7 L H L H high side direct driving The dead time is internally set at 320 ns as the typical value of the STGIPN3H60A lt 20 60 Doc ID 022726 Rev 2 AN4043 Note lt Electrical characteristics and functions Table 8 Interlocking function truth table of the STGIPN3H60 Logic input V Condition SEE IA A In ena L x X L L half bridge tri state Interlocking half bridge tri state O logic state half bridge tri state 1 ogle ag 4 L L H L low side direct driving 1 7 age state 7 H H H L H high side direct driving X not important The dead time is internally set at
12. by the internal comparator pin CIN to detect short circuit current The shunt resistor should be selected to meet the detection levels matched for the specific application An RC filter typically 1 us should be connected to the CIN pin to eliminate noise The connection length between the shunt resistor and CIN pin should be minimized If a voltage signal higher than the specified VeeF see datasheet is applied to this pin the SLLIMM nano automatically shuts down and the SD OD pin is pulled down to inform the microcontroller Shutdown open drain only for the STGIPN3H60 Pins SD OD There are two available pins of SD OD which are exactly the same They are placed on the opposite ends of the package in order to offer higher flexibility to the PCB layout It is sufficient to use only one of the two pins for the proper functioning of the device The SD OD pins work as enable disable pins The signal logic of SD OD pins are active low The SLLIMM nano shuts down if a voltage lower than a specific threshold is applied to these pins leading each half bridge in tri state The SD OD status is connected also to the internal comparator status Section 2 3 6 Short circuit protection and smart shutdown function When the comparator triggers the SD OD pin is pulled down acting as a FAULT pin The SD OD when pulled down by the comparator are open drain configured The SD OD voltage should be pulled up to the 3 3 V or
13. e Avoid any ground loop Only a single path must connect two different ground nodes e Place each RC filter as close as possible to the SLLIMM nano pins in order to increase their efficiency e In order to prevent surge destruction the wiring between the smoothing capacitor and the P and N pins should be as short as possible The use of a high frequency high voltage non inductive capacitor about 0 1 or 0 22 uF between the P and N pins is recommended e Fixed voltage tracks such as GND or HV lines can be used to shield the logic and analog lines from the electrical noise produced by the switching lines e g U V and W e Generally it is recommended to connect each half bridge ground in a star configuration and the three Rsense very close to each other and to the power ground Doc ID 022726 Rev 2 51 60 Design and mounting guidelines AN4043 In Figure 34 general suggestions for all SLLIMM nano products are summarized Figure 34 General suggestions S gnal ground and power ground mustbe connected at only one point Use of low inductance type resistor star connections avoiding long connections such as S M one can help to Plaseensure a safety distances between ground tracks and noisy tracks further decrease the paras itic high voltage or high frequency signals tracks inductance 07 Shunt resistor Power GND N w MID TD i Decoupling VB ootw i capacitor Bus capacitor V4 ay NY V Mig ooTv tite Layer1 L
14. for advanced current sensing three integrated bootstrap diodes interlocking function undervoltage lockout open emitter configuration for individual phase current sensing very compact and fully isolated package integrated gate resistors for IGBT switching speed optimum setting gate driver proper biasing lt Doc ID 022726 Rev 2 7 60 Inverter design concept and SLLIMM nano solution AN4043 Figure 3 shows the block diagram of the SLLIMM nano included in the inverter solution Figure 3 SLLIMM block diagram Mains e a TAE Gate driver pes M las Half bridge Comparator id wn OpP Amp Gate driver Microcontroller psa Meno os Half bridge Comparator LA Op Amp Gate driver e adn e Half bridge Smart Comparator Sahiba Op Amp AM10490v1 The power devices IGBTs and freewheeling diodes incorporated in the half bridge block are tailored for a motor drive application delivering the greatest overall efficiency thanks to the optimized trade off between conduction and switching power losses and very low EMI generation as a result of reduced dV dt and di dt The IC gate drivers have been selected in order to meet two levels of functionality giving users more freedom to choose a basic version which includes the essential features for a cost effective solution and a fully featured version which provides advanced options for a sophisticated control method The fully isolated NDIP package offers a high compactnes
15. input for V Low side logic input for V phase LINy LING phase active high active low Not connected Comparator input 15 NC 3D O Riobeonnected Shutdown logic input active low open drain comparator output 16 LIN UNG Low side logic input for U Low side logic input for U phase j U phase active high active low 38 60 Doc ID 022726 Rev 2 lt AN4043 Package Table 10 Input and output pins continued Description ess IGN II AS High side bias voltage pins high side bias voltage reference Pins Vbootu U Vbootv V Vbootw W The bootstrap section is designed to realize a simple and efficient floating power supply in order to provide the gate voltage signal to the high side IGBTs e The SLLIMM nano family integrates the bootstrap diodes This helps users to save costs board space and number of components The advantage of the ability to bootstrap the circuit scheme is that no external power supplies are required for the high side IGBTs e Each bootstrap capacitor is charged from the VCC supply during the on state of the corresponding low side IGBT e To prevent malfunction caused by noise and ripple in supply voltage a good quality low ESR low ESL filter capacitor should be mounted close to these pins e The value of bootstrap capacitors is strictly related to the application conditions Please consult Section 2 3 11 Bootstrap circuit for more information Gate driver bias voltage Pins Vec u Voc v
16. of the A D converter The typical scheme and principle waveforms are shown in Figure 19 Figure 19 General advanced current sense scheme and waveforms EE Sense voltage signal lload x Rs Shifted and centered signal Amplified signal Voltage required to C OUT Half bridge shifting Voltage gain make the required by the ADC current sensing of the V cance and filtering op amp stable for sampling purpose AM09339v1 lt Doc ID 022726 Rev 2 29 60 Electrical characteristics and functions AN4043 ADCs used in vector control applications have a typical full scale range FSR of about 3 3 V The sense signals must be shifted and centered on FSR 2 voltage about 1 65 V and amplified with a gain which provides the matching between the maximum value of the sensed signal and the FSR of the ADC Some typical examples of sense network sizing can be found in the user manuals listed see References 5 and References 6 2 3 11 Bootstrap circuit In the 3 phase inverter the emitters of the low side IGBTs are connected to the negative DC bus Vpc as common reference ground which allows all low side gate drivers to share the same power supply while the emitter of high side IGBTs is alternately connected to the positive Vpc and negative Vpc DC bus during the running conditions A bootstrap method is a simple and cheap solution to supply the high voltage section This function is normally accomplished by a high voltage fast re
17. to many parameters such as voltage current and temperature so it is necessary to use the same assumptions of conduction power losses Section 4 1 Conduction power losses to simplify the calculations Under these conditions the switching energy losses are given by Equation 26 Eon 8 on cos 8 6 Equation 27 Eott 8 E off cos 0 6 where E and Egg are the maximum values taken at Timax and stands for wt and y is the phase angle between output voltage and current Finally the switching power losses per device depend on the switching frequency fsw and they are calculated as follows Equation 28 Tio 2 1 E Epiodae Pas E esT Epiode wd0 SB1 Diode sw a T o o where Eiegrt and Epiode are the total switching energy for the IGBT and the freewheeling diode respectively Also in this case the total switching losses per inverter are six times this value Figure 28 shows the real turn on and turn off waveforms of the STGIPN3H60 under the following conditions Vpn 300 V Io 0 5 A Tj 100 C with inductive load on full bridge topology taken on the low side IGBT The green plots represent instantaneous power as a result of IC in red and Vce in yellow waveforms multiplication during the switching transitions The areas under these plots are the switching energies computed by graphic integration thanks to the digital oscilloscope Doc ID 022726 Rev 2 45 60 Power losse
18. wet conditions Storage e Donot force or load external pressure on the modules while they are in storage Humidity should be kept within the range of 40 to 75 the temperature should not go over 35 C or below 5 C e Lead solder ability is degraded by lead oxidation or corrosion So using storage areas where there is minimal temperature fluctuation is highly recommended The presence of harmful gases or dusty conditions is not acceptable for storage e Use antistatic containers Electrical shock and thermal injury e Donot touch either module or heatsink when the SLLIMM nano is operating to avoid sustaining an electrical shock and or a burn injury Doc ID 022726 Rev 2 ky AN4043 General handling precaution and storage notices 6 1 Packaging specifications Figure 40 Packaging specifications of NDIP 26L package AM10474v1 Nr 17 units per tube 8313150_A fy 03 PVC ANTISTATIC S 532 1 N Y ANNAN EAA LLLLLLLL a GW LLLILLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL LLL N r N 4 lt L NO R Sect A A lt Doc ID 022726 Rev 2 57 60 References AN4043 7 References AN3338 application note STGIPN3H60A datasheet STGIPNSH60 datasheet AN2738 application note UM1483 user manual UM1517 user manual Minimum Loss Strategy for Three Phase PWM Rectifier IEEE JUNE 1999 E I Note SLLIMM and PowerMESH are trademarks of STMicroelectronics
19. 0 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Inverter motor drive block diagram 1 0 cc eee ee eee 6 Discrete based inverter vs SLLIMM nano solution comparison 2005 7 SLLIMM DIGCK diagrami s vias da saab as ad owe Aa eon e ness 8 SLLIMM nano nomenclature 0 0 ee ee eens 9 Internal circuit of the STGIPNSH60A 2 ees 10 Internal circuit of the STGIPNSH60 0 0 ee ees 11 Stray inductance components of output Stage n aana aa aaea ee 13 High voltage gate drive die image ce ee eee eee 16 High voltage gate driver block diagram 0 cc ee ee eee 17 Logic input configuration for the STGIPNSH60A 0 ee 18 Logic input configuration for the STGIPNSH60 0 0 ee 18 Timing chart of undervoltage lockout function 0 0 00 ees 20 Timing chart of dead time function 0 0 ce eee ene 22 Smart shutdown equivalent Circuitry 2 0 ee eee 24 Timing chart of smart shutdown function 0 0 0 cee eee eee 25 Examples of SC protection Circuit 0 0 0 aoa eee eee 26 Example Ol oC EVENT escusa pets tapas aed eee aa esa 28 3 Phase SyS ENI ecosport ase pl ea 29 General advanced current sense scheme and WaveforMS o oooooooooooooo 29 BOOTS tad GICUI sssi rrise toreari ert te B erodes de Gee Se Ak Se SS io OA he e a 30 Bootstrap capacitor vs switching frequ
20. 180 ns as typical value In Figure 13 the details of dead time and interlocking function management of the STGIPN3H6O0 is described Doc ID 022726 Rev 2 21 60 Electrical characteristics and functions AN4043 Figure 13 Timing chart of dead time function 2 3 5 22 60 CONTROL SIGNAL EDGES OVERLAPPED INTERLOCKING DEAD TIME CONTROL SIGNALS EDGES SYNCHRONOUS DEAD TIME CONTROL SIGNALS EDGES NOT OVERLAPPED BUT INSIDE THE DEAD TIME DEAD TIME CONTROL SIGNALS EDGES NOT OVERLAPPED OUTSIDE THE DEAD TIME DIRECT DRIVING HIN and LIN can be connected together and driven by just one control signal DTL ells HVG gate driver outputs OFF d gate driver outputs OFF _ HALF BRIDGE TRI STATE HALF BRIDGE TRI STATE gate driver outputs OFF gate driver outputs OFF HALF BRIDGE TRI STATE i HALF BRIDGE TRI STATE DTLH DTHL HVG 4 h gt I gate driver outputs OFF gt gate driver outputs OFF L HALF BRIDGE TRI STATE HALF BRIDGE TRI STATE I LIN l I I I l l I I I l HIN i I I Lt l i I I LVG li I I l DTLH l DTHL l l HVG o a I gate driver outputs OFF gate driver outputs OFF 4 HALF BRIDGE TRI STATE HALF BRIDGE TRI STATE AM10496v1 Comparators for fault sensing The SLLIMM nano STGIPN3H60 integrates one comparator intended for advanced fault protection such as overcurrent overtemperature or any other type of fault measurable via a volt
21. 5 AN40A3 BT Applicatiomnote SLLIMM nano small low loss intelligent molded module By Carmelo Parisi and Giovanni Tomasello Introduction In recent years the variable speed motor control market has required high performance solutions able to satisfy the increasing energy saving requirements compactness reliability and system costs in home appliances such as dish washers refrigerator compressors air conditioning fans draining and recirculation pumps and in low power industrial applications such as small fans pumps and tools etc To meet these market needs STMicroelectronics has developed a new family of very compact high efficiency dual in line intelligent power modules with optional extra features called small low loss intelligent molded module nano SLLIMM nano The SLLIMM nano product family combines optimized silicon chips integrated in three main inverter blocks e power stage six very fast IGBTs six freewheeling diodes e driving network three high voltage gate drivers three gate resistors three bootstrap diodes e protection and optional features op amp for advanced current sensing comparator for fault protection against overcurrent and short circuit smart shutdown function dead time interlocking function and undervoltage lockout Thanks to its very good compactness the fully isolated SLLIMM nano package NDIP is the ideal solution for applications requiring reduced assem
22. 58 60 Doc ID 022726 Rev 2 ky AN4043 Revision history 8 Revision history Table 12 Document revision history omo min e 05 Apr 2012 Initial release 17 Sep 2012 gt Updated Figure 4 on page 9 Figure 17 on page 28 Figure 34 and Figure 35 on page 52 lt Doc ID 022726 Rev 2 59 60 AN4043 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein
23. A common criterion is presented here based on the following steps Defining of the overcurrent threshold value loc tp For example it can be fixed considering the IGBT typical working current in the application and adding 20 30 as overcurrent Calculation of the shunt resistor value according to the conditioning network An example of the conditioning network is shown in Figure 19 Further details can be found in the user manuals listed see References 5 and References 6 e Selection of the closest shunt resistor commercial value Calculation of the power rating of the shunt resistor taking into account that this parameter is strongly temperature dependent Therefore the power derating ratio of the shunt resistor AP T shown in the manufacturer s datasheet must be considered in the calculation as follows Equation 4 2 RSHUNT Rms PsHunt T 5 T where lpgms is the IGBT RMS working current For a proper selection of the shunt resistor a safety margin of at least 30 is recommended on the calculated power rating 2 3 9 RC filter network selection Two options of shunt 1 or 3 shunt resistor circuit can be adopted in order to implement different control techniques and short circuit protection as shown in Figure 16 Figure 16 Examples of SC protection circuit NU Rshunt u NV SHUNT V e ES E SLLIMM nano SLLIMM nano 1 shunt resistor circuit 3 shunt resistors circuit AM10499v1 An RC filter net
24. An alternative method provides a heatsink or plate bonded on the package and fixed on the PCB through a mounting screw giving higher mechanical stability as shown in Figure 39 This heatsink installation method requires a uniform layer of thermal grease or thermal rubber layer and needs a safety distance between the heatsink and the lateral side of the SLLIMM nano where some cut pins appear Doc ID 022726 Rev 2 ky AN4043 Design and mounting guidelines Figure 39 Cooling technique heatsink bonded on the PCB Heatsink Thermal grease or thermal rubber 100 200 um thickness SLLIMM nano PCB Mounting scre w Keep safety distance between heatsink and cut pins AM11828v1 Finally a large variety of solutions may exist which take advantage of the metal box in which the board can eventually be housed Nevertheless whatever the heatsink installation method may be some precautions should be observed to maximize the effect of the heatsink Smoothen the surface by removing burrs and protrusions it is essential to ensure an optimal contact between the SLLIMM nano and the heatsink Apply a uniform layer of silicon grease or thermal conductive glue from 100 um up to 200 um of thickness between the device and the heatsink to reduce the contact thermal resistance Be sure to apply the coating thinly and evenly taking care to not have any voids remaining on the contact surface between the SLLIMM nano and the heatsink We recommen
25. FF is SET dominant oscillations of the SD pin are avoided if the fault signal remains steady at a high level Timing chart of short circuit protection and smart shutdown function With reference to Figure 15 the short circuit protection is based on the following steps e tt when the output current is lower than the max allowed level the SLLIMM nano is working in normal operation e t2 when the output current reaches the max allowed level lsc the overcurrent short circuit event is detected and the protection is activated The voltage across the shunt resistor and then on the Cy pin exceeds the Vper value the comparator triggers setting the device in shutdown state and both its outputs are set to low level leading the half bridge in tri state The smart shutdown switches off the IGBT gate HVG LVG through a preferential path 200 ns as typical internal delay time and at the same time it switches on the M1 internal MOSFET The SD signal starts the discharge phase and its value drops with a time constant Ta The time constant Ta value is given by 24 60 AN4043 Electrical characteristics and functions Equation 2 TA Ron_op Rsp Csp e 13 the SD signal reaches the lower threshold Vsa THR and the control unit switches off the input HIN and LIN The smart shutdown is disabled M1 off and SD can rise up with a time constant Tp given by Equation 3 tg Rsp sp e t4 when the SD signal reaches the upper threshold Vsa y T
26. HR the system is re enabled Figure 15 Timing chart of smart shutdown function Time Constants SD discharge time Ta Ron_op Rgp C gp SD recharge time RC circuit time Tp Rep Cep constant Shutdown circuit HVG ILVG _ E HIN LIN gt E SLLIMM nano v y T gt t2 t3 t4 q AM10498v1 2 3 8 Current sensing shunt resistor selection As previously discussed the shunt resistors RsyynT externally connected between the N pin and ground see Figure 9 are used to realize the overcurrent detection When the output current exceeds the short circuit reference level lsc the C n signal overtakes the Vpep value and the short circuit protection is active For a reliable and stable operation the current sensing resistor should be a high quality low tolerance non inductive type In fact stray inductance in the circuit which includes the layout the RC filter and also the shunt resistor must be minimized in order to avoid undesired short circuit detection For these reasons the shunt resistor and the filtering components must be placed as close as possible to the SLLIMM nano pins for additional suggestions refer to Section 5 1 Layout suggestions lt Doc ID 022726 Rev 2 25 60 Electrical characteristics and functions AN4043 The value of the current sense resistor can be calculated by following different guidelines functions of the design specifications or requirements
27. LIMM nano solution Motor drive applications ranging from a few tens of watts to mega watts are mainly based on the inverter concept thanks to the fact that this solution can meet efficiency reliability size and cost constraints required in a number of markets As shown in Figure 1 an inverter for motor drive applications is basically composed of a power stage mainly based on IGBTs and freewheeling diodes a driving stage based on high voltage gate drivers a control unit based on microcontrollers or DSPs some optional sensors for protection and feedback signals for controls The approach of this solution with discrete devices produces high manufacturing costs associated with high reliability risks bigger size and higher weight a considerable number of components and the significant stray inductances and dispersions in the board layout Inverter motor drive block diagram Bridge rectifier Microcontroller Gate driver Power stage 6 60 AM09323v1 In recent years the use of intelligent power modules has rapidly increased thanks to the benefits of greater integration levels The new ST SLLIMM nano family is able to replace more than 20 discrete devices in a single package Figure 2 shows a comparison between a discrete based inverter and the SLLIMM nano solution the advantages of SLLIMM nano can be easily understood and can be summarized in a significantly improved design time reduced manufacturing efforts higher flexibi
28. age signal The comparator has an internal reference voltage VaeF specified in the datasheet on its inverting input see Figure 9 while the non inverting input is available on the Cin pin The comparator input can be connected to an external shunt resistor in order to implement a simple overcurrent or short circuit detection function as discussed in detail in Section 2 3 6 Short circuit protection and smart shutdown function Doc ID 022726 Rev 2 lt AN4043 2 3 6 lt Electrical characteristics and functions Short circuit protection and smart shutdown function The fully featured version of the SLLIMM nano STGIPN3H60 is able to monitor the output current and provide protection against overcurrent and short circuit conditions in a very short time comparator triggering to high low side driver turn off propagation delay tig 200 ns thanks to the smart shutdown function This feature is based on an innovative patented circuitry which provides an intelligent fault management operation and greatly reduces the protection intervention delay independently on the protection time duration which can be set as desired by the device user As already mentioned in Section 2 3 5 Comparators for fault sensing and as shown in Figure 9 the comparator input can be connected to an external shunt resistor Rsyynr in order to implement a simple overcurrent detection function An RC filter network Rsp and Cor is necessary to prevent erroneous op
29. al view of NDIP 26L package Top view P Bottom view SLLIMM nano NDIP 26L Internal view Main dimensions x 29 5 mm y4 12 5 mm body only Yo 22 mm including leads Z4 3 1 mm body only Zo 7 mm including leads Doc ID 022726 Rev 2 35 60 Package AN4043 3 2 Package outline and dimensions Figure 24 Outline drawing of NDIP 26L package b1 b3 A SS DD HHH YY JAA 0000 BIA og o0 or TS i BASE METAL Uc i i E5 lt Z 0 075 MONA SECTION F F amp G G PIN 16 PIN 1 ID 8278949 A AM11815v1 36 60 Doc ID 022726 Rev 2 AN4043 Package Table 9 Outline drawing of NDIP 26L package 3 3 Input and output pins description This paragraph defines the input and output pins of the SLLIMM nano For a more accurate description and layout suggestions please consult the relevant sections lt Doc ID 022726 Rev 2 37 60 Package AN4043 Figure 25 Pinout top view AM09368v1 Table 10 Input and output pins Description STGIPN3H60A STGIPN3H60 STGIPN3H60A STGIPN3H60 Ground 3D O Noreonseciad Shutdown logic input active low open drain comparator output LIN UNy Low side logic input for W Low side logic input for W phase id phase active high ET low Not connected Op amp non inverting input amp non inverting input UNS Low side logic
30. and low side IGBT a safety time dead time is introduced see Section 2 3 4 Dead time and interlocking function management for further details All the logic inputs are provided with hysteresis 1 V for low noise sensitivity and are TTL CMOS 3 3 V compatible Thanks to this low voltage interface logic compatibility the SLLIMM nano can be used with any kind of high performance controller such as microcontrollers DSPs or FPGAs As shown in the block diagrams of Figure 10 and Figure 11 the logic inputs have internal pull down or pull up resistors in order to set a proper logic level in the case of interruption in the logic lines If logic inputs are left floating the gate driver outputs LVG and HVG are set to low level This simplifies the interface circuit by eliminating the six external resistors therefore saving cost board space and number of components lt Doc ID 022726 Rev 2 17 60 Electrical characteristics and functions AN4043 Figure 10 Logic input configuration for the STGIPN3H60A Bootstrap driver UV detection UV detection High side Logic level shifting wa driver Shoot through prevention Z gt Low side driver AM10494v1 Figure 11 Logic input configuration for the STGIPN3H60 Bootstrap driver High side UV detection UV detection level Logic shifting 1 driver a i Po Shoot through fj prevention waa driver Shutdown Low side l p a 2p HVIC
31. ayer 2 Place anRC Place an R Cfilter directly across Bootstrap capacitor should be R educe all distances filter directly the CIN for each phase pin to located as close as possble between shunt resistors and acrossSDpin avoid false short circuit trigger to the SLLIMM nano pins SLLIMM nano power GND AM11823v1 Special attention must be paid to wrong layouts In Figure 35 and Figure 36 some common PCB mistakes are shown Figure 35 Example 1 on a possible wrong layout WRONG WRONG WRONG R ght angled track turns S ub connections and vias produce Decoupling capacitor is too far from produce a field concentration reflections especially on critical signal SLLMM nano at the inner edge tracks Prefer star connections and Connectit as close as possble to the Prefer 45 angled tracks reduce number of vias P pin Shuntresistor rt Power GND N Decoupling o power N a wa capacitor Viso to Ur MCU Phase current Lop V Vv Viv MCU Bus capacitor CIN filter Layer1 Layer 2 WRONG WRONG WRONG Long distance between C IN filter and CIN filter ground is not the CIN filter is close to high voltage SLLMM nano CIN pin It is important to same as per SLLMM nano switching track Ve 007 minimize this distance in order to reduce ground Noise will influence comparator the noise impact This may cause noise performances AM11824v1 lt 52 60 Doc ID 022726 Rev 2 AN4043 Design a
32. bly space without sacrificing thermal performance and reliability Compared to discrete based inverters including power devices and driver and protection circuits the SLLIMM nano family provides a high integrated level that means simplified circuit design reduced component count lower weight and high reliability The aim of this application note is to provide a detailed description of SLLIMM nano products providing guidelines to motor drive designers for an efficient reliable and fast design when using the new ST SLLIMM nano family September 2012 Doc ID 022726 Rev 2 1 60 www st com Contents AN4043 Contents 1 Inverter design concept and SLLIMM nano solution 5 1 1 Product SYNOPSIS o 6 1 2 Product line up and nomenclature o oooooooooomoo 8 1 3 Meral ceU e ya4e ae cee e he Ke sede Pe se Eee bee BS es 9 1 4 Absolute maximum ratingS 0 0 eee 10 2 Electrical characteristics and functions 0 0oooooooooo 14 2 1 ODO ees eee bees eee eee ee eee eee eee eee asa 14 2 2 Freewheeling diodes ccc tte 14 2 3 High voltage gate drivers 0 0 cc ees 14 2 3 1 LOGIC INDUS someras errar rap oe ee des de ote 16 2 3 2 High voltage level shift 0 0 0 0 ccc ee eee 18 2 3 3 Undervoltage lockout 0 ccc ete eee 18 2 3 4 Dead time and interlocking function management 19 2 3 5 Comparators for fault sensing 0 0 eee 21 2 3 6 S
33. c inductances along the PCB traces and can produce higher power loss and even malfunction in the control and sensing stages The compactness of the SLLIMM nano solution which offers an optimized gate driving network and reduced parasitic elements allows users to focus only on certain issues such as the ground issue or noise filter Therefore in order to avoid all the aforementioned conditions the following general guidelines and suggestions must be followed in PCB layout for 3 phase applications General suggestions PCB traces should be designed to be as short as possible and the area of the circuit power or signal should be minimized to avoid the sensitivity of such structures to surrounding noise Ensure a good distance between switching lines with high voltage transitions and the signal line sensitive to electrical noise Specifically the tracks of each OUT phase bringing significant currents and high voltages should be separated from the logic lines and analog sensing circuit of the op amp and comparator e Place the Rsense resistors as close as possible to the low side pins of the SLLIMM nano Ny Ny and Ny Parasitic inductance can be minimized by connecting the ground line also called driver ground of the SLLIMM nano directly to the cold terminal of sense resistors Use of a low inductance type resistor such as an SMD resistor instead of long lead type resistors can help to further decrease the parasitic inductance
34. covery diode The SLLIMM nano family includes a patented integrated structure that replaces the external diode It is realized with a high voltage DMOS driven synchronously with the low side driver LVG and a diode in series An internal charge pump provides the DMOS driving voltage The operation of the bootstrap circuit is shown in Figure 20 The floating supply capacitor Cgoor S charged from the Vcc supply when the Voy voltage is lower than the Vcc voltage e g low side IGBT is on through the bootstrap diode and the DMOS path with reference to the bootstrap charge current path During the high side IGBT ON phase the bootstrap circuit provides the right gate voltage to properly drive the IGBT see bootstrap discharge current path This circuit is iterated for all the three half bridges Figure 20 Bootstrap circuit Legend Bootstrap current path Bootstrap discharge current path AM11813v1 The value of the Cgoor capacitor should be calculated according to the application condition and must take the following into account e voltage across Cgoor must be maintained at a value higher than the undervoltage lockout level for the IC driver This enables the high side IGBT to work with a correct gate voltage lower dissipation and better overall performances Please consider that if 30 60 Doc ID 022726 Rev 2 ky AN4043 2 3 12 Electrical characteristics and functions a voltage below the UVLO threshold i
35. d by curve fitting an equation to the measured data Values for the individual resistors and capacitors are the variables from that equation and are defined in Table 11 for both Zi a Cauer and Foster thermal impedance models Doc ID 022726 Rev 2 ky AN4043 4 4 lt Power losses and dissipation Table 11 Cauer and Foster RC thermal network elements men tmp mernemo aga ose Power loss calculation example 333333335 As a result of power loss calculation and thermal aspects fully treated in the previous sections it is possible to simulate the maximum Ic rms Current versus switching frequency curves for a VVVF inverter using a 3 phase sinusoidal PWM and a six step 120 switching modulation to synthesize sinusoidal output currents The curves graphed in Figure 33 represent the maximum current managed by the SLLIMM nano in safety conditions when the junction temperature rises to the maximum junction temperature of 150 C for three ambient temperatures 25 50 and 75 C which is a typical operating condition to guarantee the reliability of the system These curves functions of the motor drive typology and control scheme are simulated under the following conditions e Vpn 300 V m 0 8 cos 0 6 T 150 C T 100 C fs ne 60 Hz max value of Rin 0 typical Vce san and Erot values Doc ID 022726 Rev 2 49 60 Power losses and dissipation AN4043 Figure 33 Maximum Iqpys current vs f sim
36. d using high quality grease with stable performance within the operating temperature range of the SLLIMM nano lt Doc ID 022726 Rev 2 55 60 General handling precaution and storage notices AN4043 6 56 60 General handling precaution and storage notices The incidence of thermal and or mechanical stress to the semiconductor devices due to improper handling may result in significant deterioration of their electrical characteristics and or reliability The SLLIMM nano is an ESD sensitive device and it may be damaged in the case of ESD shocks All equipment used to handle power modules must comply with ESD standards including transportation storage and assembly Transportation Be careful when handling the SLLIMM nano and packaging material Ensure that the module is not subjected to mechanical vibration or shock during transport Do not throw or drop in order to ensure that the SLLIMM nano is correctly functioning before boarding Wet conditions are dangerous and moisture can also adversely affect the packaging Hold the package in such a way as to avoid touching the leads during mounting Putting package boxes upside down leaning them at an angle or giving them uneven stress may cause the terminals to be deformed or the resin to be damaged Throwing or dropping the packaging boxes may cause the modules to be damaged Wetting the packaging boxes may cause the malfunction of modules when operating Pay attention when transporting in
37. defined as the difference in temperature between junction and ambient reference divided by the power dissipation per device Equation 30 qj Tamb Rth j a P lt Doc ID 022726 Rev 2 AN4043 Power losses and dissipation Figure 29 shows an equivalent circuit of the thermal resistance between junction and ambient Rih i a Figure 29 Rin i a equivalent thermal circuit AM11817v1 As the power loss Pot is cyclic also the transient thermal impedance must be considered It is defined as the ratio between the time dependent temperature increase above the reference AT t and the relevant heat flow Equation 31 AT t Ztp t th t Contrary to that already seen regarding the thermal resistance the thermal impedance is typically represented by an RC equivalent circuit For pulsed power loss the thermal capacitance effect delays the rise in junction temperature and therefore the advantage of this behavior is the short term overload capability of the SLLIMM nano For example Figure 30 shows thermal impedance from a junction to ambient curve for a single IGBT of the SLLIMM nano Figure 30 Thermal impedance Z curve for a single IGBT 1818v SLLIMM nano Z inj a AM1 OL A ETA U LUT AHH N TU TMI ELITE TEIN LUTTE U AUT W A A A A A U W A A A A A A L N T N N ETE N CATE TAT A ATT ATT UN ACT LT A A A N N L N U O U A T PICO A PA PA A per Lc O A iN 1 E 05 1 E 04 1 E 03 1 E 02 1 E 01
38. ency 0 000 cee eee 32 Initial bootstrap charging time nasaan eee eee nes 33 Images and internal view of NDIP 26L package 0 0 00 cee 35 Outline drawing of NDIP 26L package cc eee eee 36 PINOON VICW o2 2 lt 2cceee640505 080048 tool e e eee eee see 38 Typical IGBT power loSS S 2 ke eee eee eens 42 IGBT and diode approximation of the output characteristics 43 Typical switching waveforms of the STGIPN3H60 2 0 0 0 es 46 Rthi ay equivalent thermal Circuit 1 6 ee 47 Thermal impedance Zin j a curve for a single IGBT 6 ee ee eee eee 47 Cauer RC equivalent circuit lt 2 wu ee see ce kee iaa ane eee e ead wad ew owe ala 48 Foster RC equivalent Circuit 0 00 ee eee ee eens 48 Maximum Ic rms Current vs fsw simulated Curves 1 06 0 eee eee eee 50 General SUggeSTIONS 0 eee ee ee eee eee eens 52 Example 1 on a possible wrong layout 0 0 00 cee ees 52 Example 2 on a possible wrong layout 0 cc ee ee eens 53 Cooling technique copper plate on the PCB 2 ee 54 Cooling technique heatsink bonded on the package o o o oooooooomoo 54 Cooling technique heatsink bonded on the PCB 0 ccc ee 55 Packaging specifications of NDIP 26L package 00 eee 57 Doc ID 022726 Rev 2 5 60 Inverter design concept and SLLIMM nano solution AN4043 Figure 1 Inverter design concept and SL
39. eration of the protection The output signal of the comparator is fed to an integrated MOSFET with the open drain available on the SD OD pin shared with the SD input When the comparator triggers the device is set in shutdown state and all its outputs are set to low level leaving the half bridge in tri state In common overcurrent protection architectures the comparator output is usually connected to the SD input and an external RC network Rep and Cgp is connected to this SD OD line in order to provide a mono stable circuit which implements a protection time when a fault condition occurs Contrary to common fault detection systems the new smart shutdown structure allows an immediate turn off of the output gate driver in the case of fault without waiting for the external capacitor to be discharged This strategy minimizes the propagation delay between the fault detection event and the actual outputs switch off In fact the time delay between the fault and outputs disabling is not dependent on the RC value of the external SD circuitry but thanks to the new architecture has a preferential path internally in the driver Then the device immediately turns off the driver outputs and latches the turn on of the open drain switch until the SD signal has reached its lower threshold After the SD signal goes below the lower threshold the open drain is switched off see Figure 15 The smart shutdown system provides the possibility to increase the val
40. hort circuit protection and smart shutdown function 22 2 3 7 Timing chart of short circuit protection and smart shutdown function 23 2 3 8 Current sensing shunt resistor selection o o ooooo o 24 2 3 9 RC filter network Selection 0 0 00 ce ee ee 26 2 3 10 Op amps for advanced current sensing 0 0 00 eee aes 27 an Il BOOIStaprelnCclill so entosasorcrto rostros tada 29 2 3 12 Bootstrap capacitor selection n a naaa aa mo 30 2 3 13 Initial bootstrap capacitor charging o ooooooooomooo 32 3 s el Lo IPUR eePUU 5O5 O o Laa eoar ENER 34 3 1 Package structure 2 no 34 3 2 Package outline and dimensions ooooocoooo eee eee eens 35 3 3 Input and output pins description 2 0 0 es 36 4 Power losses and dissipation 00 cece eee eee ee 41 4 1 Conduction power lOSSES 0 tenes 41 4 2 Switching power losses 00 c cece eee eee 44 4 3 Thermal impedance overview nanana 45 2 60 Doc ID 022726 Rev 2 ky AN4043 Contents 4 4 Power loss calculation example 0000 eee eee eee 49 Design and mounting guidelines 00 0c cee eee eee 51 5 1 Layout suggestions 0 ees 51 5 1 1 General suggestions 0 ccc eee eee 51 5 2 Mounting instructions and cooling techniques ooo 53 General handling precaution and storage notices 56 6 1 Packaging specifications
41. lity in a wide range of applications and increased reliability and quality level In addition the optimized silicon chips in both control and power stages and the optimized board layout provide maximized efficiency reduced EMI and noise generation higher levels of protection and lower propagation delay time Doc ID 022726 Rev 2 ky AN4043 Inverter design concept and SLLIMM nano solution Figure 2 Discrete based inverter vs SLLIMM nano solution comparison Reduced total Passive components HV gate drivers IGBTs FWDs system cost Diodes Reduced EMI Resistors Easy layout anaes and noise Improved efficiency Advanced High quality protection and reliability function High compactness AM10489v1 1 1 Product synopsis The SLLIMM nano family has been designed to satisfy the requirements of a wide range of final applications up to 100 W in free air such as e dish washers refrigerator compressors air conditioning fans draining and recirculation pumps low power industrial applications small fans pumps and tools The main features and integrated functions can be summarized as follows eo 600V 3A ratings e 3 phase IGBT inverter bridge including six low loss IGBTs six low forward voltage drop and soft recovery freewheeling diodes e three control ICs for gate driving and protection including smart shutdown function comparator for fault protection against overcurrent and short circuit opamp
42. n be used in all applications where high voltage shifted control is necessary and it includes a patented internal circuitry which replaces the external bootstrap diode Doc ID 022726 Rev 2 15 60 Electrical characteristics and functions AN4043 16 60 Figure 8 Each high voltage gate driver chip controls two IGBTs in half bridge topology offering basic functions such as dead time interlocking integrated bootstrap diode and also advanced features such as smart shutdown patented fault comparator and a dedicated high performance op amp for advanced current sensing A schematic summary of the features by device are listed in Table 7 In this application note the main characteristics of a high voltage gate drive related to the SLLIMM nano are discussed For a greater understanding please refer to the AN2738 application note Doc ID 022726 Rev 2 AN4043 Electrical characteristics and functions Figure 9 High voltage gate driver block diagram to DC link Logic Level 4 Csoor shifter Shoot through _tomotor_ gt prevention i U V W Vee 3 Shutdown driver LVG Rsp latch C i IN from to uC i SLLIMM nano AM10493v1 2 3 1 Logic inputs The high voltage gate driver IC has two logic inputs HIN and LIN to separately control the high side and low side outputs HVG and LVG Please refer to Table 1 for the input signal logics by device In order to prevent any cross conduction between high side
43. nd mounting guidelines Figure 36 Example 2 on a possible wrong layout 5 ll Ground path Ta WRONG we Ps Very large ground loop Does not use the suggested star connection Long ground path could be affected by noise due to high voltage switching tracks and could affect driver or application performance WRONG The cold terminal of the sense resistor is not chosen as star centre te N ground SS Pp WRONG E 2 e had Connection between the a SLLIMM nano and ground is not minimized SLLIMM nano AM11825v1 5 2 Mounting instructions and cooling techniques The SLLIMM nano is a very compact intelligent power module able to drive electric motors up to 100 W without any heatsink or cooling system installed on the board The NDIP is a transfer mold package with no screw holes therefore some dedicated cooling techniques must be adopted if a higher power level is targeted One of the easiest methods is based on a natural cooling system and a proper design of the PCB layout In this case the PCB along with the pads acts as a heatsink providing paths for individual packages to effectively transfer heat to the board and the adjacent environment Therefore maximizing the area of the metal traces where the power and ground pins of the package are located is a valuable method for reducing the thermal resistance and for leading to an improved power performance The pins mainly involved in this phenome
44. non are the positive DC pin P and the phase output pins U V W since they are directly connected to the copper lead frame where the power devices are mounted and IGBTs and diodes are the major source of heat as already treated in Section 4 Power losses and dissipation Several aspects impact on the total thermal performance such as the area of metal traces the thickness of the copper plate their placement on the board and the distance between the SLLIMM nano and other heat lt Doc ID 022726 Rev 2 53 60 Design and mounting guidelines AN4043 54 60 sources Both sides of the PCB can be used and thermally connected through direct copper connections or thermal vias in order to increase the heat dissipation and reduce the layout complexity Figure 37 shows an example of a metal trace layout used to dissipate heat on the PCB Figure 37 Cooling technique copper plate on the PCB AM11826v1 SLLIMM nano Double side metal trace footprint areas connected with thermal vias Higher thermal performance can be achieved by using a large and compact external heatsink in close contact with the SLLIMM nano The heatsink can be directly fixed on the package thanks to thermal conductive glue or adhesive foil between the heatsink and the backside of the package as shown in Figure 38 Figure 38 Cooling technique heatsink bonded on the package Heatsink Thermal conductive glue or adhesive foil SLLIMM nano AM11827v1
45. oltage 0 3 to Vcc 0 3 vo Op amp non inverting input 0 3 to Vcc 0 3 MA oe opammi ata egos v or viaprotage amas CV Vn tose tag appied beeen HN UN and GND 0301s v e Vcc low voltage power supply lt Doc ID 022726 Rev 2 13 60 Inverter design concept and SLLIMM nano solution AN4043 Vcc represents the supply voltage of the control part A local filtering is recommended to enhance the SLLIMM nano noise immunity Generally the use of one electrolytic capacitor with greater value but not negligible ESR and one smaller ceramic capacitor hundreds of nF faster than the electrolytic one to provide current is suggested Please refer to Table 4 in order to properly drive the SLLIMM nano Table 4 Supply voltage and operation behavior Vcc voltage typ value Operating behavior STGIPN3H60A STGIPN3H60 As the voltage is lower than the UVLO threshold the control circuit is not fully lt 10V lt 12V i turned on A perfect functionality cannot be guaranteed 12V 17V 13 5 V 18 V Typical operating conditions gt 18 V gt 21 V Control circuit is destroyed Table 5 Total system Operating junction temperature 40 to 150 Module case operation temperature 40 to 125 14 60 Doc ID 022726 Rev 2 lt AN4043 2 2 1 2 2 2 3 Electrical characteristics and functions Electrical characteristics and functions In this section the main electrical characteristics of the power stage are discussed toge
46. or starts to charge through the low side IGBT LVG e t2 the voltage across the bootstrap capacitor Vegoor reaches its turn on undervoltage threshold Ves thon e t3 the bootstrap capacitor is fully charged this enables the high side IGBT and the Cgoor capacitor starts to discharge in order to provide the right IGBT gate charge The bootstrap capacitor recharges during the on state of the low side IGBT LVG Figure 22 Initial bootstrap charging time Vec Y DC Bus Vpy pS LVG gt Ves thon ess Ves_thorF r Ve BOOT Y 4 Time gt AM09342v1 The initial charging time is given byEquation 12 Equation 12 and must be for safety reasons at least three times longer than the calculated value Doc ID 022726 Rev 2 33 60 Electrical characteristics and functions AN4043 34 60 Equation 12 C RDS on V i gt BOOT In ee CHARGE Nao AVCBOOT where is the duty cycle of the PWM signal and Rog on iS 120 Q typical value as shown in the datasheet A practical example can be done by considering a motor drive application where the PWM switching frequency is 16 kHz with a duty cycle of 50 and AVcegoor 0 1 V that means a gate driver supply voltage Vcc 17 5 V From the graph in Figure 21 the bootstrap capacitance is 1 0 uF therefore the Cgoor can be selected by using a value between 2 0 and 3 0 uF According to the commercial value the bootstrap capacitor can be 2 2 uF From Equation
47. rop AVcgoor to guarantee when the high side IGBT is on and must be Equation 8 AVcBooT Vcc VE WRDS on VGE min VCE sat max under the condition Equation 9 VCBOOT min gt VBS _ thON where VGE min Minimum gate emitter voltage of high side IGBT Ves thon bootstrap turn on undervoltage threshold maximum value see datasheet Considering the factors contributing to Vegoor decreasing the total charge supplied by the bootstrap capacitor during high side ON phase is Doc ID 022726 Rev 2 31 60 Electrical characteristics and functions AN4043 32 60 Equation 10 QToT UGATE Ikee laBo ILK ILkDiode ILKCap tHon QLs where Qeate total IGBT gate charge l kee IGBT gate emitter leakage current logo bootstrap circuit quiescent current ILk bootstrap circuit leakage current lL KDiode bootstrap diode leakage current I_KCap bootstrap capacitor leakage current relevant when using an electrolytic capacitor but can be ignored if other types of capacitors are used tHon high side ON time Qs charge required by the internal level shifters Finally the minimum size of the bootstrap capacitor is Equation 11 QTOT CBooT AVCBOOT For an easier selection of bootstrap capacitor Figure 21 shows the behavior of Cagot calculated versus switching frequency f y with different values of AVecgoor corresponding toEquation 11 Equation 11 for a continuous sinusoidal modulation and a dut
48. s and dissipation AN4043 Figure 28 Typical switching waveforms of the STGIPN3H60 Turn on Turn off pence STGIPN3H60 ale ds Low side Low side Tj 100 C Uco Eon and Ey are the areas under the red plots B Vce Ic dt AM11816v1 4 3 46 60 Thermal impedance overview During operation power losses generate heat which elevates the temperature in the semiconductor junctions contained in the SLLIMM nano limiting its performance and lifetime To ensure safe and reliable operation the junction temperature of power devices must be kept below the limits defined in the datasheet therefore the generated heat must be conducted away from the power chips and into the environment using an adequate cooling system The SLLIMM nano was designed to drive electric motors up to 100 W without any heatsink Therefore the thermal aspect of the system is one of the key factors in designing high efficiency and high reliability equipment In this environment the package and its thermal resistance play a fundamental role Thermal resistance quantifies the capability of a given thermal path to transfer heat in steady state and it is generically given as the ratio between the temperature increase above the reference and the relevant power flow Equation 29 Rin th AP The thermal resistance specified in the datasheet is the junction ambient Rih j a which is commonly used with natural and forced convection air cooled systems and it is
49. s applied on the bootstrap channel the IC disables itself no output without any fault signal e the voltage across Cgoor is affected by different components such as drop across the integrated bootstrap structure drop across the low side IGBT and others e when the high side IGBT is on the Cgoor capacitor discharges mainly to provide the right IGBT gate charge but other phenomena must be considered such as leakage currents quiescent current etc Bootstrap capacitor selection A simple method to properly size the bootstrap capacitor considers only the amount of charge that is needed when the high voltage side of the driver is floating and the IGBT gate is driven once This approach does not take into account either the duty cycle of the PWM or the fundamental frequency of the current Observations on PWM duty cycle the kind of modulation 6 step 12 step and sine wave must be considered with their own peculiarity to achieve the best bootstrap circuit sizing During the bootstrap capacitor charging phase the low side IGBT is on and the voltage across Cgoor Vcegoor can be calculated as follows Equation 7 VcBootT Vcc VF VaDS on VCE sat max where Vcc supply voltage of gate driver Ve bootstrap diode forward voltage drop VCE sat max Maximum emitter collector voltage drop of low side IGBT Vrps on DMOS voltage drop The dimension of the bootstrap capacitance Cgoor value is based on the minimum voltage d
50. s level very useful in those applications with reduced space ensuring at the same time high thermal performance and reliability levels lt 8 60 Doc ID 022726 Rev 2 AN4043 Inverter design concept and SLLIMM nano solution 1 2 Product line up and nomenclature Table 1 SLLIMM nano line up tag Y o o y 3 3 5 V input interface compatibility Figure 4 SLLIMM nano nomenclature sarn Special features A Basic version L1 Single phase G 30 IGBT Diode Vers Voltage divided by 10 Technology SLLIMM IPM K H High frequency 8 20 kHz W Very High frequency 15 50 kHz Package C Medium frequency 4 10 kHz L SDIP 38L molded Nominal current N NDIP 26L molded S SDIP 25L molded I current at To 25 C AM09343v2 lt Doc ID 022726 Rev 2 9 60 Inverter design concept and SLLIMM nano solution 1 3 Figure 5 LIN U NC HIN U Vcc U NC LIN V HIN V Vcc V NC NC NC LIN W HIN W Vcc W NC GND 10 60 AN4043 Internal circuit Internal circuit of the STGIPN3H60A lt Vkboot U gt Cc IN E ZN AA IK ES ZN AA N U Vboot V A lt 18 A a o lt Vboot W BANES 25 lt J ywy gt IN Eh ZS z 26 SU lt lt _ Nw AM09369v 1 lt Doc ID 022726 Rev 2 AN4043 Figure 6 CIN LIN V HIN V Vcc Y OP OPOUT D LIN W HIN W Vcc W 1 4 lt In
51. sses switching losses and off state losses and they are essentially generated by the power devices of the inverter stage such as the IGBTs and the freewheeling diodes The conduction losses Pconp are the on state losses during the conduction phase The switching losses Psw are the dynamic losses encountered during turn on and turn off The off state losses due to the blocking voltage and leakage current can be neglected Finally the total power losses are given by Equation 14 Prot Peond Pew Figure 26 shows a typical waveform of an inductive hard switching application such as a motor drive where the major sources of power losses are specified Figure 26 Typical IGBT power losses taon conduction tech lt gt AM09357v1 4 1 Conduction power losses The conduction losses are caused by IGBT and freewheeling diode forward voltage drop at rated current They can be calculated using a linear approximation of the forward characteristics for both the IGBT and diode having a series connection of DC voltage source representing the threshold voltage V o for IGBT and Ve y for diode and a collector emitter on state resistance Reg and anode cathode on state resistance Rax as shown in Figure 27 42 60 Doc ID 022726 Rev 2 ky AN4043 Power losses and dissipation Figure 27 IGBT and diode approximation of the output characteristics AMO9345v1 Tc 150 C 13V Tc 125 C Rak AV rm Alen
52. tarts to turn off the SLLIMM nano e 3 the SD in activated e 4 the SLLIMM nano is definitively turned off in 580 ns including the tg of time of IGBT from SC detection Finally the total disable time is t4 t2 and the total SC action time is t4 t1 Doc ID 022726 Rev 2 27 60 Electrical characteristics and functions AN4043 Figure 17 Example of SC event 580ns Example of SC event kl to DC link to motor RsHunt SLLIMM nano AM11812v2 2 3 10 Op amps for advanced current sensing The fully featured version of the SLLIMM nano STGIPN3H60 integrates also one operational amplifier optimized for field oriented control FOC applications In a typical FOC application the currents in the three half bridges are sensed using a shunt resistor The analog current information is transformed into a discontinuous sense voltage signal having the same frequency as the PWM signal driving the bridge The sense voltage is a bipolar analog signal whose sign depends on the direction of the current see Figure 18 lt 28 60 Doc ID 022726 Rev 2 AN4043 Electrical characteristics and functions Figure 18 3 phase system 3 phase driver Sensing Sinusoidal Vector Control Discontinuous Voltage at fpwy frequency lload x Rs lload x Rs IPHASE NY AM09338v1 The sense voltage signals must be provided to an A D converter They are usually shifted and amplified by dedicated op amps in order to exploit the full range
53. tations which can generate some surge voltages the maximum surge voltage between P N Ven surge allowed is lower than Vcgs as shown in Figure 7 At the same time considering also the surge voltage generated by the stray inductance between the device and the DC link capacitor the maximum supply voltage in steady state applied between P N Vpy must be even lower than Vpn surge Thanks to the small package size and the lower working current this phenomenon is less marked in the SLLIMM nano than in a big intelligent power module lt Doc ID 022726 Rev 2 AN4043 Inverter design concept and SLLIMM nano solution Figure 7 Stray inductance components of output stage The real voltage over the IGBT Due to di dt value and parasitic can exceed the rating voltage inductance the over voltage spike can appear on the SLLIMM pins VPN surge High di dt value to motor gt U V W 4 l l l l l l l l l l l l l l l l l l l l SLLIMM nano A 4 I l l Parasitic inductance Parasitic inductance due to the SLLIMM internal layout due to PCB layout AM10492v1 e lc each IGBT continuous collector current The allowable DC current continuously flowing at the collector electrode Tc 25 C The lc parameter is calculated according to Equation 7 Table 3 Control part of the STGIPN3H60 Output voltage applied between OUT OUTy OUT yy and Low voltage power supply 0 3 to 21 Comparator input v
54. ther with a detailed description of all the SLLIMM nano functions IGBTs The SLLIMM nano achieves power savings in the inverter stage thanks to the use of IGBTs manufactured with the proprietary advanced PowerMESH process These power devices optimized for the typical motor control switching frequency offer an excellent trade off between voltage drop VcE sat and switching speed tra and therefore minimize the two major sources of energy loss conduction and switching reducing the environmental impact of daily use equipment A full analysis on the power losses of the complete system in reported in Section 4 Power losses and dissipation Freewheeling diodes Turbo 2 ultrafast high voltage diodes have been adequately selected for the SLLIMM nano family and carefully tuned to achieve the best t VF trade off and softness as freewheeling diodes in order to further improve the total performance of the inverter and significantly reduce the electromagnetic interference EMI in the motor control applications which are quite sensitive to this phenomena High voltage gate drivers The SLLIMM nano is equipped with a versatile high voltage gate driver IC HVIC designed using BCD offline Bipolar CMOS and DMOS technology see Figure 8 and particularly suited to field oriented control FOC motor driving applications able to provide all the functions and current capability necessary for high side and low side IGBT driving This driver ca
55. ue of the external RC network across the SD pin sized to fix the disable time generated after the fault event as much as desired by the user without compromising the intervention time delay of the SLLIMM nano protection A block diagram of the smart shutdown architecture is depicted in Figure 14 Doc ID 022726 Rev 2 23 60 Electrical characteristics and functions AN4043 2 3 7 Figure 14 Smart shutdown equivalent circuitry SLLIMM nano Except for STGIPS10K60A AM10497v1 In normal operation the outputs follow the commands received from the respective input signals When a fault detection event occurs the fault signal FSD is set to HIGH by the fault detection circuit output and the FF receives a SET input signal Consequently the FF outputs set the SLLIMM nano output signals to low level and at the same time turn on the open drain MOSFET which works as active pull down for the SD signal Note that the gate driver outputs stay at low level until the SD pin has experienced both a falling edge and a rising edge although the fault signal may be returned to low level immediately after the fault sensing In fact even if the FF is reset by the falling edge of the SD input the SD signal also works as enable for the outputs thanks to the two AND ports Moreover once the internal open drain transistor has been activated due to the latch it cannot be turned off until the SD pin voltage reaches the low logic level Note that since the
56. ulated curves 3 phase sinusoidal PWM AM11821v1 AAA T o T SO E ES ESA OOOO T S S ee Syr A tt y 300 V Modulation Index 0 8 Pot tT Th TT TI PF 0 6 T 150 C fine 60 Hz C CCO E e OL T OT T AO T T MO AMO MO O MO O O O lc RMs A AAAA TA AAAY A il l l l l l l l l ree ATA i j i al i l a AM11822v1 mie 300 V Modulation Index 0 8 PF gt 0 6 1 190 C fan 60Hz duty cycle 60 MT 25 C bee __ it Pe eee _ _ 3 lp lc RMS A lt 50 60 Doc ID 022726 Rev 2 AN4043 5 5 1 5 1 1 Design and mounting guidelines Design and mounting guidelines This section introduces the main layout suggestions for an optimized design and major mounting recommendations to appropriately handle and assemble the SLLIMM nano family Layout suggestions Optimization of PCB layout for high voltage and high switching frequency applications is a critical point PCB layout is a complex matter as it includes several aspects such as length and width of track and circuit areas but also the proper routing of the traces and the optimized reciprocal arrangement of the various system elements in the PCB area A good layout can help the application to properly function and achieve the expected performance On the other hand a PCB without a careful layout can generate EMI issues both induced and perceived by the application can provide overvoltage spikes due to parasiti
57. ver outputs when the supply voltage goes below the Vcc thorr threshold specified on the datasheet and turns on the IC when the supply voltage goes above the Vcc mon voltage A hysteresis of about 1 5 V is provided for noise rejection purposes The high voltage floating supply Vboot is also provided with a similar undervoltage lockout circuitry When the driver is in UVLO condition both gate driver outputs are set to low level setting the half bridge power stage output to high impedance The timing chart of undervoltage lockout plotted in Figure 12 is based on the following steps e ti when the Vcc supply voltage raises the Vcc thon threshold the gate driver starts to work after the next input signal HIN LIN is on The circuit state becomes RESET e t2 input signal HIN LIN is on and the IGBT is turned on e 13 when the Vcc supply voltage goes below the Vcc thorr threshold the UVLO event is detected The IGBT is turned off in spite of input signal HIN LIN The state of the circuit is now SET e 14 the gate driver re starts once the Vcc supply voltage again raises the Vcc thon threshold e t5 input signal HIN LIN is on and the IGBT is turned on again lt Doc ID 022726 Rev 2 19 60 Electrical characteristics and functions AN4043 Figure 12 Timing chart of undervoltage lockout function Vcc thon Time gt AM09332v1 2 3 4 Dead time and interlocking function management In order to prevent any possible cross conduction
58. verter design concept and SLLIMM nano solution Internal circuit of the STGIPN3H60 V BOOT AK ip ha AM09365v1 Absolute maximum ratings The absolute maximum ratings represent the extreme capability of the device and they can be normally used as a worst limit design condition It is important to note that the absolute maximum value is given according to a set of testing conditions such us temperature frequency voltage and so on Device performance can change according to the applied condition Doc ID 022726 Rev 2 11 60 Inverter design concept and SLLIMM nano solution AN4043 12 60 The SLLIMM nano specifications are described below using the STGIPN3H60 datasheet as an example Please refer to the respective product datasheets for a detailed description of all possible types Table 2 Inverter part Each IGBT continuous collector current at Tc 25 C BA Each IGBT pulsed collector current BA Each IGBT total dissipation at Tc 25 C PB Pw 1 Applied between HINy HINy HINw LINy LINy LINw and GND 2 Calculated according to the iterative Equation 1 3 Pulse width limited by max junction temperature Equation 1 oo ee Rth j c VCE sat max OT max Ic Tc eo Vces collector emitter voltage The power stage of the SLLIMM nano is based on IGBTs and freewheeling diodes having 600 V Vces rating Generally considering the intelligent power module internal stray inductances during the commu
59. work is required to prevent undesired short circuit operation due to the noise on the shunt resistor 26 60 Doc ID 022726 Rev 2 ky AN4043 lt Electrical characteristics and functions Both solutions allow to detect the total current in all three phases of the inverter The filter is based on the Rss and Cor network and its time constant is given by Equation 5 tsF RsF Csr In addition to the RC time constant the turn off propagation delay of the gate driver tisd specified in the datasheet and the IGBT turn off time in the range of tens of ns must be considered in the total delay time trota which is the time necessary to completely switch off the IGBT once the short circuit event is detected Therefore the trata is calculated as follows Equation 6 Total IsF tisd loft and the tof is recommended to be set in the range of 1 2 us In the case of a 3 shunt resistor circuit a specific control technique can be implemented by using the three shunt resistors Rgyyunt_u RsHunt v and Rsyunt w able to monitor each phase current An example of a short circuit event is shown in Figure 17 where it is possible to note the very fast protection thanks to the smart shutdown function against fault events The main steps are e t1 collector current IC starts to rise SC event is not detected yet due to the RC network on the Cin pin e 12 voltage on Vey reaches the Vpcrr SC event is detected and the smart shutdown s
60. y cycle 6 50 Figure 21 Bootstrap capacitor vs switching frequency AM11814v1 STGIPN3H60A STGIPN3H60 6 50 AV csoor 0 1V AV cpoot 0 3V LL xe L O O O O m O Doc ID 022726 Rev 2 ky AN4043 2 3 13 lt Electrical characteristics and functions Considering the limit cases during the PWM control and further leakages and dispersions in the board layout the capacitance value to use in the bootstrap circuit must be selected two or three times higher than the Cgoor calculated in the graph of Figure 21 The bootstrap capacitor should be with a low ESR value for a good local decoupling therefore in case an electrolytic capacitor is used one parallel ceramic capacitor placed directly on the SLLIMM nano pins is strictly recommended Initial bootstrap capacitor charging During the startup phase the bootstrap capacitor must be charged for a suitable time to complete the initial charging time tcharce which is at least the time Vcgoor needs to exceed the turn on undervoltage threshold Vgs thon as already stated in Equation 9Equation 9 For a normal operation the voltage across the bootstrap capacitor must never drop down to the turn off undervoltage threshold Ves norF throughout the working conditions For the period of startup only the low side IGBT is switched on and just after this phase the PWM is run as shown in the following steps of Figure 22 e ti the bootstrap capacit

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SLLIMM™-nano small low-loss intelligent molded module