PLBv46 PCI Using the RaggedStone1 Evaluation Board
Contents
1. X1057_11_012408 Figure 11 pci_dma c output Running the The selection of the hello_pci project is shown in Figure 12 Make the hello_pci project active Applications and the remaining software projects inactive 4 xiling Platform Studio homefesters designs mls55_mb_plbv46_pci system xmp System Assembly View2 5 x File Edit View Project Hardware Software Device Configuration Debug Simulation Window Help lalx DP able tgloa y a Alanga Ali B Llam AR el ela lE BB 0a al Bus Interfaces Ports Addresses Se BiF Filters Project Applications 1p Catal ae alj 6 e e Software Projects microblaze_O microblaze 7 00 a E Add Software Application Project ilmb Imb_v10 1 00 a Default microblaze_0_bootloop dimb Imb_v10 1 00 a Default microblaze_0_xmdstub mb_plb plb_v46 1 00 a R dimb_cntir Imb_bram_if 2 10 a i Processor microblaze_O ilmb_cntlr Imb_bram_if 2 10 a f xecutable home lesters design xps_bram_if_cntlr_1 xps_bram_if 1 00 a Compiler Options gt mb_bram bram_block 1 00 a i ources gt xps_bram_if_cntlr bram_block 1 00 a i Headers PLEDs_SBit xps_gpio 1 00 a Project dma_pci xps_intc_O xps_intc 1 00 a Processor microblaze_0 gt clk_diff_buf ibufgds_buf 1 00 a xecutable home lesters design debug_module mdm 1 00 a ompiler Options PRS232_Uart_l xps_uartlite 1 00 a plbv46_pci_O plbv46_pci 1 01 a lt proc_sys_2. Configuration Address Port Register Definitions Bit Definition 0 5 Target word address in configuration space 6 7 Hardwired to 0 8 12 Device 13 15 Function 16 23 Bus Number 24 Enable 25 31 Hardwired to 0 XAPP1057 v1 0 April 3 2008 www xilinx com Reference System Specifics Reference System Specifics XAPP1057 v1 0 April 3 2008 XILINX In addition to the MicroBlaze processor and PLBv46 PCI this system includes BRAM memory UART MDM XPS Central DMA and interrupt controller The PCI Arbiter core is included in the FPGA RaggedStone1 Spartan 3 FPGA PCI Evaluation Board In the reference design the PLBv46 PCI in the XC3S1500 on the RaggedStone1 Spartan 3 Evaluation Board interfaces to the PLBv46 PCI in the Virtex 4 ML410 Evaluation Board Table 2 provides the address map for the XC3S1500 Table 2 RaggedStone1 Spartan 3 Address Map Peripheral Instance Base Address High Address XPS UART Lite RS232_Uart_1 0x84000000 0x8400FFFF PLBv46 PCI plbv46_pci_O 0x42600000 0x4260FFFF MDM debug_module 0x84400000 Ox8440FFFF XPS INTC xps_intc_0O 0x81800000 Ox8180FFFF XPS CENTRAL DMA xps_central_dma_0O 0x81810000 Ox8181FFFF XPS BRAM xps_bram_if_cntlr_1 Ox8AE08000 Ox8AEOFFFF The RaggedStone1 Spartan 3 1500 Evaluation Board includes a 64 bit PCI edge connector RS232C port LED displays Atmel 512K x 8 AT49BV040A Flash Memory and a JTAG port The MicroBlaz
3. Bus Master Enable bit is set and the latency timer is set to avoid time outs If the v3 0 core latency timer remains at the default 0 value configuration writes to remote PCI devices do not complete and configuration reads of remote PCI devices terminate due to the latency timer expiration Configuration reads of remote PCI devices with the latency timer set to O return OXFFFFFFFF www xilinx com 5 Reference System Specifics XAPP1057 v1 0 April 3 2008 ML410 XC4VFX60 Address Map The address map of the ML410 XC4VFX60 is shown in Table 3 Table 3 ML410 XC4VFX60 System Address Map XILINX Peripheral Instance Base Address High Address MPMC3 DDR_SDRAM_32Mx64 0x00000000 Ox03FFFFFF XPS UART16550 RS232_Uart_1 0x83E00000 0x83E0FFFF XPS INTC XPS_INTC_O 0x81800000 Ox8180FFFF PLBv46_PCl PCI32_Bridge 0x85E00000 Ox85E0FFFF XPS Central DMA xps_central_dma_0O 0x80200000 Ox8020FFF XPS BRAM xps_bram_if_cntlr_O OxFFFFO000 OxFFFFFFFF XPS GPIO LEDs_8Bit 0x81400000 0x8140FFFF XPS SysAce SysACE_CompactFlash 0x83600000 0x8360FFFF XPS IIC IIC_Bus 0x81600000 0x8160FFFF RaggedStone1 Spartan 3 PLBv46 PCI Generics The reference design contains the following settings for Spartan 3 PLBv46 PCI generics C_FAMILY spartan3 C_INCLUDE_PCI_CONFIG 0 C_INCLUDE_BAROFFSET 0 C_IPIFBAR_NUM 2 C_PCIBAR_NUM 2 C_IPIFBAR_0O 0x20 000000 C_IPIFBAR2PCIBAR_0 0x80000000 C_IPIFBAR_1 0xE8000000 C_IPIFB
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5. for viewing in the ModelSim waveform viewer The vcd file can be opened in the Cadence Design System Inc Simvision design tool by selecting File Open Database eh ChipScope Pro Analyzer new project File View JTAG Chain Device TriggerSetup Waveform Window Help O atl eo Fle eB if r 4 New Project l E waveform DEW 1 MyDevice1 XC4VFX60 UNIT 0 MyiLAO ILA JTAG Chain Sa DEV 0 MyDeviceO System_ACE_CF Bus Signal xo DEV 1 MyDevicet XC4VFX60 f UNITO MYILAD ILA gt PCI32 BRIDGE PCI CBE Trigger Setup PCI32_BRIDGE PCI_FRAME_N Waveform Listing PCI32_BRIDGE PCI_DEVSEL_N Bus Plot PCI32_BRIDGE PCI_TRDY_N PCI32_BRIDGE PCI_IRDY_N Signals DEV 1 UNIT 0 Data Port j PCI32_BRIDGE PCI_STOP_W LJ IPCI32_BRIDGEIPCI_CBE E flo yper3e BRIDGE PCI aD A EE S ERDOERA AA PCI32_BRIDGE PCI 3 noooo0o0 X X000 X 00000000 X Oooo X JPCI32_BRIDGE PLB_WrDBu 4PCI32 BRIDGE PLB_WrDBuS D2062200 IPCI32_BRIDGE SI_RdDBus amp JPCI32_BRIDGE PLB_ABus CH 0 plb_PLB_PAValid PCI32 BRIDGE PLB ABUS 00000004 CH 1 fplb_PLB_wrPendReq p CH 2 plb_PLB_rdBurst CH 3 Jplb_PLB_busLock CHA NAN D PNKAt a hal Sait 83200 LT A x 0 iQ PCI32_BRIDGE S1_RdDBus 00000000 a COMMAND set_match_function 10 0 0 3 1 XXXXXXXXXXXIXXXXXXXXXXX COMMAND set_trig
6. gt XILINX XAPP1057 v1 0 April 3 2008 Summary Included Systems Required Hardware and Tools Application Note Embedded Processing Reference System PLBv46 PCI Using the RaggedStone1 Evaluation Board Author Lester Sanders This application note describes how to build a reference system for the Processor Local Bus Peripheral Component Interconnect PLBv46 PCI core using the MicroBlaze processor based embedded system in the RaggedStone1 Evaluation Board The RaggedStone1 Evaluation Board uses the Spartan 3 FPGA and has a PCI connector A set of files containing Xilinx Microprocessor Debugger KMD commands is provided for writing to the Configuration Space Header and for verifying that the PLBv46 PCI core is operating correctly Two software projects illustrate how to configure the PLBv46 PCI cores set up interrupts scan configuration registers and set up and use DMA operations The procedure for using ChipScope Pro Analyzer to analyze PLBv46 PCI functionality is provided This application note includes one reference system www xilinx com support documentation application_notes xapp1057 zip The project name used in xapp1057 zip is rs1_mb_plbv46_pci Users must have the following tools cables peripherals and licenses available and installed EDK provides an evaluation license for PLBv46 PCI e Xilinx EDK 9 2 02i e Xilinx ISE 9 2 04i e Xilinx Download Cable Board Cable USB or Parallel Ca
7. 00 Of fset 20 00000000 Offset 24 00000000 Offset 28 00000000 Offset 2C BEEFBODE Offset 30 00000000 Offset 34 00000000 Offset 38 00000000 Offset 30 543201FF Enable Master Transactions on Xilinx PCI Core Status Command Reg of Kilinx PCI Core 02000546 Set Max LAT Timer on Xilinx PCI Core Status Reg xC in Xilinx PCI Core G000FFOO Set Bus Num and Subordinate bus Num on Xilinx PCI Core Bus Num Sub Bus Num Reg 0x114 in Xilinx PCI Core 01000000 Scan PCI Config Regs of South Bridge AD18 Of fset 00 153310B9 Offset 04 0210000F Offset 08 06010000 Offset 0C 90000000 Of fset 10 00000000 Offset 14 00000008 Offset 18 00000000 Offset 1C 00000000 Of fset 20 00000000 Offset 24 00000000 Offset 28 00000000 Offset 20 153310B9 Of fset 30 00000000 Offset 34 000000A8 Offset 38 00000000 Offset 3C 00000000 Connected 0 01 04 Auto detect 9600 8 N 1 sh APS NUM X1057_14_012408 Figure 14 Running hello_pci XAPP1057 v1 0 April 3 2008 www xilinx com 14 Using ChipScope with PLBv46 PCI XILINX Using Because of limited JTAG BSCAN resources using ChipScope Inserter in a Spartan 3 FPGA ChipScope with usually results in overmapping errors To avoid these errors the ICON and the IBA and ILA PLBv46 PCI cores are included in the MHS file and the design is implemented just as when the ChipScope cores are not included Figure 15 shows the use of ChipScope cores in the MHS file BEGIN chipscope_ icon PARAMETER INSTANCE c
8. AR2PCIBAR_1 0x90000000 When C_FAMILY is defined as Virtex4 or Spartan3 the PLBv46 PCI uses the v3 0 PCI LogiCORE IP When C_FAMILY is defined as Virtex5 the PLBv46 PCI uses the v4 0 PCI LogiCORE IP www xilinx com Reference System Specifics x XILINX Figure 5 shows how to specify the values of the Base Address Registers BARs in EDK aplbv46_per_0 plbv46_pci_v1_01_a i HDL 2 Toggle Names Datasheet Restore IPIF BARO Base Address fx20000000 IPIF BARO High Address bx2Perrrrr Remote PCI device BAR to which IPIF BARO is translated when configured with FIFOs xs0000000 IPIF BARO Memory Designator M IPIF BAR1 Base Address pxze000000 IPIF BAR1 High Address pxESPEEEFE Remote PCI device BAR to which IPIF BAR1 is translated when configured with FIFOs px900000000 IPIF BAR1 Memory Designator Remote PCI device BAR to which IPIF BAR2 is translated when configured with FIFOs px00000000 x1057_05_032408 Figure 5 Specifying the Values of Base Address Register Generics in EDK Since the ML410 does the configuration in this setup set C_INCLUDE_PCI_CONFIG to 0 When C_INCLUDE_BAR_OFFSET 0 the C_IPIFBAR2PCIBAR_ generic s are used in address translation instead of IPIFBAR2PCIBAR_ registers Setting C_IPIFBAR_NUM 2 specifies that there are two address ranges for PLB to PCI transactions Setting C_PCIBAR_NUM 2 specifies that two address ranges are used for PCI to PLBv46 transactions Fig
9. I Bus signals for PClI_Monitor 12 43 and rename it PCI AD Note The Reverse Bus Order operation is useful for analyzing bus signals 1 Setthe trigger in the Trigger Setup window The trigger used depends on the problem being debugged For example if debugging a configuration transaction from the ML410 PLB trigger on an PLB address of C_BASEADDR 0x10C If debugging a problem configuring from the PCI side trigger on the PCI_Monitor 44 47 for a configuration write on PCI_CBE Change the Windows to N samples to a setting of 500 Arm the trigger by selecting Trigger Setup gt Arm or clicking on the Arm icon 2 Run XMD or GDB to activate trigger patterns which cause ChipScope to display meaningful output For example set the trigger to PA_Valid 1 and run xmd tcl 410 s3 tcl atthe command prompt www xilinx com 16 Using ChipScope with PLBv46 PCI XILINX 3 ChipScope results are analyzed in the waveform window as shown in Figure 16 This figure shows the original PCl_monitor lt gt signals and the PCI_monitor_ad signal generated The waveforms may be easier to read if the discrete PCI_monitor lt gt signals are removed after they are renamed To share the results with other users save the results in the waveform window as a Value Change Dump vcd file The vcd files can be translated and viewed in most simulators The vcd2wlf translator in ModelSim reads a vcd file and generates a ModelSim waveform log file wIf file
10. _Monitor signals are the PCI bus signals AD CBE and the remaining PCI Bus signals Table 5 defines the functionality of the PCI_Monitor signals The Filter Pattern PCI_Monitor is used to locate the PCI bus signals Table 5 PCI Monitor Signals Bit Position PCI Signal 0 FRAME_N 1 DEVSEL_N TRDY_N IRDY_N STOP_N IDSEL_int INTA PERR_N SERR_N Req_N_toArb PAR 11 REQ_N 12 43 AD 44 47 CBE O O N OO oa A OJIN K To begin debugging invoke ChipScope Pro Analyzer by selecting Start Programs gt ChipScope Pro gt ChipScope Pro Analyzer Click on the Chain icon located at the top left of Analyzer GUI Verify that the message in the transcript window indicates that an ICON is found The ChipScope Analyzer waveform viewer displays signals named DATA To replace the DATA signal names with the signal names select File Import and enter the ila and iba cdc files from the implementation directory in the dialog box The Analyzer waveform viewer is more readable when buses rather than discrete signals are displayed Select the PLB_ABus lt gt signals click the right mouse button and select Add to Bus New Bus With PLB_ABus lt 0 31 gt in the waveform viewer select and remove the 32 discrete PLB_ABus lt gt signals Repeat this for the PLB data buses Make PCI Bus signals by creating a new bus for PClI_Monitor 44 47 Rename PCI_Monitor 44 47 PCI_CBE Make PC
11. ble IV e Model Technology ModelSim v6 1e e ChipScope 9 2 01 e PLBv46 PCI License e RaggedStone1 Evaluation Board 2008 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc All other trademarks are the property of their respective owners XAPP1057 v1 0 April 3 2008 www xilinx com 1 Introduction Introduction XAPP1057 v1 0 April 3 2008 XILINX PCI transactions are done between an initiator and a target This reference design is for the RaggedStone1 Spartan 3 Evaluation Board To be useful it must be inserted into a PCI slot In the examples provided in this application note the RaggedStone1 Spartan 3 Evaluation Board is inserted into PCI slot P3 of the Xilinx ML410 Evaluation Platform This allows both configuration and memory transactions to be done on the PCI bus between an initiator and a target The examples use the ML410 PLBv46 PCI as the initiator and the RaggedStone1 Spartan 3 Evaluation Board PLBv46 PCI as the target It is relatively easy to modify the examples so that the initiator and target functions are swapped Figure 1 is a functional diagram of the RaggedStone1 Board interfacing to the ML410 Evaluation Platform RaggedStone1 PLBv46 PLBv46 PCI PCI PLI Slot P3 X1057_01_012408 Figure 1 Interfacing RaggedStone1 Spartan 3 PLBv46 PCI with ML410 PLBv46 PCI www xilinx com 2 XILINX Introduction Figur
12. e 2 is the RaggedStone1 Evaluation Board cas Giap CAS CA4C16 oe 183 wo wo A N N 5 ww ta Tig LEOS masti LIA MAX pm Su N E U20 216 RAGGEDSTONE J uwy enter point co Uk Ons REV 1 2 L3 EYAN AANT ann RaggedStone1 Evaluation Board X1057_02_012408 Figure 2 www xilinx com XAPP1057 v1 0 April 3 2008 Introduction Figure 3 is a block diagram of the reference system XPS XPS BRAM UARTLITE CNTR MicroBlaze Processor XPS PLBv46 CENTRAL DMA PCI X1057_03_012408 Figure 3 RaggedStone1 Spartan 3 PLBv46 PCI Reference System Block Diagram The RaggedStone1 Spartan 3 Evaluation Board has a PCI edge connector on one side of the board Three variations of the RaggedStone1 Spartan 3 Evaluation Board differ in the use of the XC3S400 XC3S1000 or XC3S1500 each in a 456 pin package The functions devices and buses in this PLBv46 PCI reference design are addressed using the Configuration Address Port format shown in Figure 4 00 Doubleword Function No Bus No Reserved i i Device No Figure 4 Configuration Address Port Format The Configuration Address Port and Configuration Data Port registers in the host bridge PLBv46 PCI Bridge are used to configure multiple PCI bridges when host bridge configuration is enabled The bit definitions of the Configuration Address Port in the big endian format used by the PLB are given in Table 1 Table 1
13. e microprocessor runs at 75 MHz The application note XAPP1001 Reference System PLBv46 PCI in a ML410 Embedded Development Platform provides a link to the hardware design files used for the ML410 Configuration of the PLBv46 PCI on the ML410 Board The PLBv46 PCI bridge uses the 32 bit Xilinx LogiCORE PCI32 Interface v3 0 core For the PLBv46 PCI bridge to perform transactions on the PCI bus the v3 0 core must be configured using configuration transactions from either the PCl side or the PLBv46 side In this system the ML410 PLBv46 PCI is the host bridge and it configures itself and then configures the RaggedStone1 Spartan 3 Evaluation Board PLBv46 PCI The C_INCLUDE_PCI_CONFIG parameter is set to 1 The IDSEL input of the v3 0 is connected to address ports and the PLBv46 PCI IDSEL port is unused To configure the XC4VFX60 with the bitstream connect the Xilinx download cable to the ML410 JTAG port and use Impact to download the ML410 download bit file Do the following steps to write to the configuration header 1 Configure the Command and Status Register The minimum that must be set is the Bus Master Enable bit in the command register For memory transactions set the memory space bit For I O transactions set the I O space bit 2 Configure the Latency Timer to a non zero value 3 Configure at least one BAR Configure subsequent BARs as needed for other memory lO address ranges The v3 0 core configures itself only after the
14. ger_condition 10 3 15555 COMMAND set_storage_condition 1 0 FFFF COMMAND run 10 COMMAND upload 10 INFO Device 1 Unit 0 Waiting for core to be armed Upload X1057_16_012408 Figure 16 ChipScope Analyzer Results XAPP1057 v1 0 April 3 2008 www xilinx com 17 References References Revision History Notice of Disclaimer XAPP1057 v1 0 April 3 2008 XILINX DS207 PCI 64 32 Interface v3 0 Data Sheet UG159 LogiCORE IP Initiator Target v3 1 for PCI UG262 LogiCORE IP Initiator Target v4 5 for PCI UG085 ML410 Embedded Development Platform User Guide UG044 ChipScope ILA Tools Tutorial UG241 OPB PCI v1 02a User Manual XAPP1001 PLBv46 PCI Using the ML410 Embedded Development Platform XAPP998 PCI Bus Performance Measurements using the Vmetro Bus Analyzer RaggedStone1 User Manual Issue 1 03 4 1 2006 Enterpoint Ltd oC ONnNonPr oN The following table shows the revision history for this document Date Version Revision 4 03 08 1 0 Initial Xilinx release Xilinx is disclosing this Application Note to you AS IS with no warranty of any kind This Application Note is one possible implementation of this feature application or standard and is subject to change without further notice from Xilinx You are responsible for obtaining any rights you may require in connection with your use or implementation of this Application Note XILINX MAKES NO REPRESENTATIONS OR WARRANTIES
15. goutfile Writing Ox086002002 to M410 CSR at O0x42600110 puts goutfile mwr Ox42600110 Ox86002002 puts goutfile Reading L410 COP at O0x42600110 CSR Expecting Ox46C puts goutfile mrd Ox42600110 1 puts goutfile Writing Ox06400060 to M1410 CAP OC Rev ID puts goutfile mwr Ox4260010C 0x08400080 puts goutfile Reading L410 Class Code Rey ID puts goutfile mrd Ox42600110 1 puts goutfile Writing ML410 Ox0C400060 LT puts goutfile mwr Ox4260010C 0x0C400080 puts goutfile Writing ML410 Ox0O0FFO000 to LT COP puts goutfile mwr Ox42600110 0x00FF0000 puts goutfile Reading ML410 COP at Ox42600110 Expecting LT 0x0C puts goutfile mrd Ox42600110 1 puts goutfile Writing Ox10400080 ML410 BARO CAP puts goutfile mwr Ox4260010C 0x10400080 puts goutfile Writing ML410 BARO Ox60000000 puts goutfile mwr Ox42600110 Ox00000060 a ee 2 So be ae AA Figure 7 XMD Commands Used in Configuration XAPP1057 v1 0 April 3 2008 www xilinx com 10 Reference System Specifics x XILINX XAPP1057 v1 0 April 3 2008 Software Projects The reference system contains the following software projects hello_pci This project enables master transactions sets the latency timer defines the bus number subordinate bus number and scans the PCI bus configuration space headers pci_dma This project runs DMA operations The user sets the source address destination address and DMA length This code is used for DMA operatio
16. he configuration header Configure the Command Register Latency Timer and BAR s of the other devices in the system 4 Read the configuration headers of the other devices in the system 5 Perform a memory read of one of the IPIF BARs 6 Perform a memory write of one of the IPIF BARs Verification is done using either Xilinx Microprocessor Debugger XMD or the software projects discussed later TCL scripts using XMD commands are provided in the rsl_mb_plbv46_pci xmd_commands directory The 410_s3 tcl script configures and verifies the ML410 and Spartan 3 PLBv46 PCI cores To run this script connect the Platform CABLE_USB cable to the ML410 JTAG connector and enter xmd tcl xmd_commands 410 s3 tcl atthe command prompt The XMD commands in the 410_s3 tcl file partially listed in Figure 7 write to the Configuration Address Port and the Configuration Data Port to program the Configuration Space Header The Command Status Register Latency Timer and Base Address Registers are written and read www xilinx com 9 Reference System Specifics x XILINX vE Konsole lt 2 gt Muts outfile Configure the ML410 PLB PCI puts goutfile Writing Ox00400080 to ML410 CAP Device ID endor IC puts goutfile mwr Ox4260010C 0x00400060 puts goutfile Reading COP at Ox42600110 Device ID Vendor ID puts goutfile mrd Ox42600110 1 puts goutfile Writing Ox04400060 to ML410 CAP CSR puts goutfile mwr Ox4260010C 0x04400080 puts
17. hipscope_icon_0 PARAMETER HW_VER 1 01 a PARAMETER C_ NUM CONTROL PORTS PARAMETER C_ SYSTEM CONTAINS MDM 1 PORT controlO chipscope plbv46 iba 0 icon ctrl ORT controll chipscope plbv46 iba _0 icon ctrl END BEGIN chipscope_ila PARAMETER INSTANCE chipscope_ila_0 PARAMETER HW _VER 1 01 a PARAMETER C_TRIGO UNITS 1 PARAMETER C_TRIGO_TRIGGER_IN WIDTH PARAMETER C_ NUM DATA SAMPLES 512 PARAMETER C_ DATA SAME AS TRIGGER PARAMETER C_ DATA IN WIDTH 50 PARAMETER C_ENABLE TRIGGER _OUT 1 PARAMETER C ENABLE TRIGGER OUT 0 PORT chipscope_ila_control chipscope_ila_0_icon_control PORT DATA PCI_monitor amp RS232 Interrupt amp CDMA Interrupt PORT CLK sys_clk_s PORT TRIGO PCI_monitor 0 amp CDMA Interrupt amp mb_plb_ PLB PAValid amp mb_plb PLB MAddrAck PORT TRIGO PCI monitor 0 END BEGIN chipscope plbv46_iba PARAMETER INSTANCE chipscope_plbv46_iba_0 PARAMETER HW_VER 1 00 a PARAMETER PARAMETER PARAMETER PARAMETER BUS_INTER PORT chip PORT PLB END Figure 15 C_NUM_ DATA SAMPLES C_USE_MU_5 RD DBUS C_USE_MU_4 WR _DBUS C_MU_1 TRIG IN WIDTH FACE MON PLB mb_plb scope_icon_control Clk sys_clk_s 512 1 chipscope plbv46 iba _0 icon ctrl Instantiating ChipScope cores in MHS file X1057_15_012408 XAPP1057 v1 0 April 3 2008 www xilinx com 15 Using ChipScope with PLBv46 PCI XILINX XAPP1057 v1 0 April 3 2008 The PCI
18. itstream impact batch etc xapp1057 cmd 3 Invoke XMD and connect to the MicroBlaze processor xmd opt etc xapp1057 opt 4 While the PLBv46 PCI in the RaggedStone1 board can act as the host bridge this reference design uses the PLBv46 PCI in the ML410 as the host bridge Connect the JTAG cable to the ML410 Download the bitstream Download the executable dow m1410 ppc plbv46 pci ready for download hello pci elf Executing the Reference System from EDK To execute the system using EDK follow these steps 1 Select File Open Project system xmp Select Hardware Generate Bitstream to generate a bitstream Download the bitstream to the board using Device Configuration Download Bitstream 4 Invoke XMD with Debug gt Launch XMD 5 While the PLBv46 PCI in the RaggedStone1 board can act as the host bridge this reference design uses the PLBv46 PCI in the ML410 as the host bridge Connect the JTAG cable to the ML410 Download the bitstream Download the executable using command dow m1410 ppc plbv46 pci ready for download hello pci elf www xilinx com 8 Reference System Specifics x XILINX XAPP1057 v1 0 April 3 2008 Verifying the Reference Design with the Xilinx Microprocessor Debugger After downloading the bitstream file and writing to the configuration header verify that the RaggedStone1 Spartan 3 reference design is set up correctly 1 Configure the v3 0 Command Register Latency Timer and BAR s 2 Read t
19. ns between a variety of source and destination addresses Figure 8 shows some of the parameters in pci_dma c which can be edited to run DMA transactions between different memory regions define MEM 0 BASEADDR 0x20000000 define MEM 1 BASEADDR 0x20002000 DMALength 1024 X1057_08_012408 Figure 8 Defining Source and Destination Addresses Length in pci_dma c DMA Transactions Many of the XMD scripts and C code examples generate Direct Memory Access DMA operations DMA transactions are initiated by writing to the Control Source Address Destination Address and Length registers of the DMA controller Table 4 provides these register locations of the XPS Central DMA controller Table 4 XPS Central DMA Registers Control Register C_BASEADDR 0x04 Source Address Register C_BASEADDR 0x08 Destination Address Register C_BASEADDR 0x0C Length Register C_BASEADDR 0x10 www xilinx com 11 Reference System Specifics x XILINX An example of XMD code which generates DMA transactions is given in Figure 9 Write DMA Control Register mwr 0x80200004 OxC0000004 Write DMA Source Address Register mwr 0x80200008 0x20000000 Write DMA Destination Address Register mwr O0x8020000C 0x20002000 Write DMA Length mwr 0x80200010 64 X1057_09_012408 Figure 9 Generating DMA Transactions The pci_dma c code consists of the four functions in the functional diagram in Figure 10 1 The Barber
20. pole Region function provides a rotating data pattern on the memory located at the source address 2 The Zero Region function sets the memory located at the destination address to all zeroes 3 The DMA Region function performs a DMA transaction of data located at the source address to the memory at the destination address 4 The Verify function verifies that data at the source address and destination address are equal Barberpole Zero Region X1057_10_012408 Figure 10 Functional Diagram of pci_dma c XAPP1057 v1 0 April 3 2008 www xilinx com 12 Running the Applications x XILINX Figure 11 show the Hyperterminal output when running the pci_dma executable elf t HyperTerminal File Edit View Call Transfer Help De s3 on f Entering BarberPoleRegion StartAddress 20000000 Length 00000100 Exiting BarberPoleRegion Entering ZeroRegion Entering main DMA example MEM_ StartAddress 20000000 MEM_1 StartAddress 20002000 Entering BarberPoleRegion StartAddress 20000000 Length 00000100 Exiting BarberPoleRegion Entering ZeroRegion Entering main DMA example MEM_6 StartAddress 20000000 MEM_1 StartAddress 20002000 Entering BarberPoleRegion StartAddress 20000000 Length 00000400 Exiting BarberPoleRegion Entering ZeroRegion Connected 18 10 00 Auto detect 9600 8 N 1
21. reset_O proc_sys_reset 2 00 a DDR2_SDRAM_32 mpmc 3 00 a gt clock_generator_O clock_genera 1 00 a xps_central_dma_O xps_central_ 1 00 a System Assembly View be Pj X1057_12_012408 Figure 12 Selecting the hello_pci Software Project XAPP1057 v1 0 April 3 2008 www xilinx com 13 Running the Applications x XILINX With hello_pci selected right click to build the project Connect a serial cable to the RS232C port on the ML410 board Start a HyperTerminal session Set Bits per second to 9600 Data bits to 8 Parity to None and Flow Control to None as shown in Figure 13 COM1 Properties Port Settings Bits per second Data bits Parity Stop bits Flow control Restore Defaults X1057_13_012408 Figure 13 HyperTerminal Parameters From XPS start XMD and enter connect ppc hwandrst atthe XMD prompt Invoke GDB and select Run to start the application as shown in Figure 14 The hello_pci c code originally written for the ML310 Embedded Development Platform runs without any modifications on this reference system t HyperTerminal De es 28 PCI Test PCI Test Scan PCI Config Regs of ML41 Xilinx PCI Core AD24 Of fset 00 030010EE Offset 04 02000546 Offset 08 0680001N Offset OC O080FFOO Of fset 10 60000008 Offset 14 A0000008 Offset 18 00000000 Offset 10 000000
22. ure 6 provides a functional diagram of the PLBv46 PCI core The functions in the PLBv46 PCI are the PLBv46 Master PLBv46 Slave v3 0 PCI Core and the IPIF v3 0 Bridge XAPP1057 v1 0 April 3 2008 www xilinx com 7 Reference System Specifics x XILINX XAPP1057 v1 0 April 3 2008 PLBv46 Master IPIF v3 0 v3 0 Bridge PCI Core PCI PLBV46 PLBv46 I I I I I I I I I I I Slave I I I X1057_06_012408 Figure 6 PLBv46 PCI Functional Diagram Configuration of PLBv46 PCI on the RaggedStone1 Evaluation Board When the RaggedStone1 Spartan 3 FPGA Board is inserted into the ML410 PCI slot P3 the PLBv46 PCI Bridge in the XC4VFX60 FPGA interfaces to an PLBv46 PCI Bridge in the XC3S1500 FPGA on the RaggedStone1 Spartan 3 Board To configure the XC3S1500 connect the Xilinx download cable to the RaggedStone1 Spartan 3 FPGA Board JTAG port and use Impact to download the rsl_mb plbv46 pci ready for _download download bit file After downloading the XC3S1500 FPGA bit file the PCI functionality in the XC3S1500 PLBv46 PCI is configured using Configuration write PCI transactions from the ML410 PLBv46 PCI Executing the Reference System using the Pre Built Bitstream and the Compiled Software Applications Use the steps below to execute the system using files inside the rsl mb plbv46 pci ready for download directory 1 Change to the rs1_mb plbv46 pci ready for download directory 2 Use iMPACT to download the b
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