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TEWS Technologies TIP866 Manual

1. to OxBF Offset in Read Write Size Bit Comment IP I O Space 0x11 LSB of Divisor Latch DLL 8 LCR bit 7 set to 1 but OxBF 0x13 MSB of Divisor Latch DLM 8 LCR bit 7 set to 1 but OxBF 0x15 Enhanced Feature Register EFR 8 LCR set to 0xBF 0x17 Line Control Register LCR 8 Always accessible 0x19 Xon 1 Word 8 LCR set to OxBF 0x1B Xon 2 Word 8 LCR set to OxBF 0x1D Xoff 1 Word 8 LCR set to OxBF Ox1F Xoff 2 Word 8 LCR set to OxBF Table 4 5 Channel 2 Register Set 2 TIP866 User Manual Issue 1 0 9 Page 11 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 4 1 3 Channel 3 Register Set After reset Register Set 1 is selected TEWSS TECHNOLOGIES Register Set 1 is accessible if bit 7 of the Line Control Register LCR Offset 0x27 is set to 0 Offset in Read Mode Write Mode Size Bit IP I O Space 0x21 Receive Holding Register RHR Transmit Holding Register THR 8 0x23 Interrupt Enable Register IER Interrupt Enable Register IER 8 0x25 Interrupt Status Register ISR FIFO Control Register FCR 8 0x27 Line Control Register LCR Line Control Register LCR 8 0x29 Modem Control Register MCR Modem Control Register MCR 8 0x2B Line Status Register LSR 8 0x2D Modem Status Register MSR 8 0x2F Not used Not used 8 Table 4 6 Channel 3 Register Set 1 Register Set
2. A rtisan Artisan Technology Group is your source for quality TecmologyGrap new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF Instra zer REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED EE Contact us 888 88 SOURCE sales artisantg com www artisantg com TEWSS The Embedded I O Company TECHNOLOGIES TIP866 8 Channel Serial Interface IP Version 1 0 User Manual Issue 1 0 9 February 2009 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 Phone 49 0 4101 4058 0 9190 Double Diamond Parkway Phone 1 775 850 5830 25469 Halstenbek Germany Fax 49 0 4101 4058 19 Suite 127 Reno NV 89521 USA Fax 1 775 201 0347 www tews com e mail info tews com www tews com e mail usasales tews com Artisan Technology Group Quality Instrumentation
3. DLL registers e Modify DLM DLL registers e Write normal operation byte value to LCR register The MCR Modem Control Register bits 5 7 must be enabled for modifying by setting EFR Enhanced Feature Register bit 4 These steps should be used to modify MCR bit 7 Write 0xBF to LCR register enable access to EFR register Set EFR register bit 4 to 1 enable modification of MCR bits 5 7 Write 0x00 to LCR register enable access to MCR register Modify MCR bit 7 Write 0xBF to LCR register enable access to EFR register Set EFR register bit 4 to 0 Latch MCR bit setting Write normal operation byte value to LCR register TIP866 User Manual Issue 1 0 9 Page 22 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 6 Pin Assignment I O Connector 6 1 50 pin I O connector TIP866 10 ET RS232 11 ET TTL Pin Signal TIP866 10 ET Comment Comment RS232 TIP866 10 ET RS232 TIP866 11 ET TTL Signal TIP866 11 ET TTL GND Signal Ground GND Signal Ground 11 GND Signal Ground 16 GND Signal Ground 21 GND Signal Ground 26 GND Signal Ground 31 GND Signal Ground 33 RXD7 Active low Active high SINIJA AJIN gt TIP866 User Manual Issue 1 0 9 Page 23 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES Pin Signal T
4. Guaranteed 888 88 SOURCE www artisantg com TIP866 10 8 channel RS232 serial I O TIP866 10 ET 8 channel RS232 serial I O for operating temperature 40 C to 85 C TIP866 11 8 channel TTL serial I O TIP866 11 ET 8 channel TTL serial temperature 40 C to 85 C I O for operating TIP866 20 8 channel RS422 serial I O TIP866 20 ET 8 channel RS422 serial I O for operating temperature 40 C to 85 C TIP866 User Manual Issue 1 0 9 TEWSS TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP_RESET Access terms are described as W Write Only R Read Only R W Read Write R C Read Clear R S Read Set 1996 2009 by TEWS TECHNOLOGIES GmbH All trademarks mentioned are property of their respective owners Page 2 of 26 Arti
5. TIP866 User Manual Issue 1 0 9 Page 8 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 4 IP Addressing All registers for the eight serial channels and three special registers of the TIP866 are accessible in the IP I O space Register Address Offset in IP I O Space Channel 1 Register Set 0x00 to 0xOF Channel 2 Register Set 0x10 to Ox1F Channel 3 Register Set 0x20 to 0x2F Channel 4 Register Set 0x30 to Ox3F Channel 5 Register Set 0x40 to Ox4F Channel 6 Register Set 0x50 to Ox5F Channel 7 Register Set 0x60 to Ox6F Channel 8 Register Set 0x70 to Ox7F INTVEC OxOF FIFORDY1 Ox1F FIFORDY2 Ox5F Table 4 1 UO Space Address Map The three special registers INTVEC FIFORDY1 and FIFORDY2 are located within the register sets of channels 1 2 and 6 4 1 Channel Register Sets Each of the eight I O channels is controlled by two register sets register set 1 and register set 2 mapped to the Quad UART ST16C654 registers The Line Control Register LCR is common to both register sets of a channel Bit 7 of the Line Control Register is used to select the actual register set 1 or 2 for a channel For more details on the ST16C654 registers and programming please see the ST16C654 data sheet TIP866 User Manual Issue 1 0 9 Page 9 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 S
6. but OxBF 0x73 MSB of Divisor Latch DLM 8 LCR bit 7 set to 1 but OxBF 0x75 Enhanced Feature Register EFR 8 LCR set to 0xBF 0x77 Line Control Register LCR 8 Always accessible 0x79 Xon 1 Word 8 LCR set to 0xBF 0x7B Xon 2 Word 8 LCR set to 0xBF 0x7D Xoff 1 Word 8 LCR set to OxBF Ox7F Xoff 2 Word 8 LCR set to 0xBF Table 4 17 Channel 8 Register Set 2 TIP866 User Manual Issue 1 0 9 Page 17 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 4 2 Special Registers 4 2 1 Interrupt Vector Register Offset 0x0F The Interrupt Vector Register INTVEC is a byte wide read write register It is located within the Register Set 1 of Channel 1 Each Quad UART controller generates an individual interrupt Quad UART Controller 1 for channel 1 4 and Quad UART Controller 2 for channel 5 8 The Interrupt Vector Register is shared between both interrupt sources Bit Symbol Description Access Reset Value 7 1 Interrupt vector loaded by software R W all 0 0 In UO space always read as 1 R For INT vector cycle Read as 0 for an interrupt from controller 1 channel 1 4 Read as 1 for an interrupt from controller 2 channel 5 8 Example INTVEC loaded with 0x60 Controller 1 will create interrupt vector 0x60 Controller 2 will create interrupt vector 0x61 Table 4 18 Interrupt V
7. 2 is accessible if bit 7 of the Line Control Register LCR Offset 0x27 is set to 1 The Enhance Feature Register Xon 1 2 and Xoff 1 2 registers are accessible only when LCR is set to OxBF Offset in Read Write Size Bit Comment IP I O Space 0x21 LSB of Divisor Latch DLL 8 LCR bit 7 set to 1 but OxBF 0x23 MSB of Divisor Latch DLM 8 LCR bit 7 set to 1 but OxBF 0x25 Enhanced Feature Register EFR 8 LCR set to OxBF 0x27 Line Control Register LCR 8 Always accessible 0x29 Xon 1 Word 8 LCR set to OxBF 0x2B Xon 2 Word 8 LCR set to OxBF 0x2D Xoff 1 Word 8 LCR set to OxBF Ox2F Xoff 2 Word 8 LCR set to OxBF Table 4 7 Channel 3 Register Set 2 TIP866 User Manual Issue 1 0 9 Page 12 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 4 1 4 Channel 4 Register Set After reset Register Set 1 is selected TEWSS TECHNOLOGIES Register Set 1 is accessible if bit 7 of the Line Control Register LCR Offset 0x37 is set to 0 Offset in Read Mode Write Mode Size Bit IP I O Space 0x31 Receive Holding Register RHR Transmit Holding Register THR 8 0x33 Interrupt Enable Register IER Interrupt Enable Register IER 8 0x35 Interrupt Status Register ISR FIFO Control Register FCR 8 0x37 Line Control Register LCR Line Control Register LCR 8 0x39 Modem
8. Control Register MCR Modem Control Register MCR 8 0x3B Line Status Register LSR 8 0x3D Modem Status Register MSR 8 Ox3F Not used Not used 8 Table 4 8 Channel 4 Register Set 1 Register Set 2 is accessible if bit 7 of the Line Control Register LCR Offset 0x37 is set to 1 The Enhance Feature Register Xon 1 2 and Xoff 1 2 registers are accessible only when LCR is set to OxBF Offset in Read Write Size Bit Comment IP I O Space 0x31 LSB of Divisor Latch DLL 8 LCR bit 7 set to 1 but OxBF 0x33 MSB of Divisor Latch DLM 8 LCR bit 7 set to 1 but OxBF 0x35 Enhanced Feature Register EFR 8 LCR set to OxBF 0x37 Line Control Register LCR 8 Always accessible 0x39 Xon 1 Word 8 LCR set to OxBF 0x3B Xon 2 Word 8 LCR set to OxBF 0x3D Xoff 1 Word 8 LCR set to OxBF Ox3F Xoff 2 Word 8 LCR set to OxBF Table 4 9 Channel 4 Register Set 2 TIP866 User Manual Issue 1 0 9 Page 13 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 4 1 5 Channel 5 Register Set After reset Register Set 1 is selected TEWSS TECHNOLOGIES Register Set 1 is accessible if bit 7 of the Line Control Register LCR Offset 0x47 is set to 0 Offset in Read Mode Write Mode Size Bit IP I O Space 0x41 Receive Holding Register RHR Transmit Holding Register THR 8 0
9. connectors mounted in a 6U 4TE front panel TIP866 10 RS232 only TIP866 20 RS422 only i Figure 1 1 Block Diagram TIP866 User Manual Issue 1 0 9 Page 6 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 2 Technical Specification IP Interface Single Size IndustryPack Logic Interface compliant to ANSI VITA 4 1995 8MHz Wait States No wait states Interrupts Vectored interrupts IP_INTREQO for I O channels 1 4 IP INTREQ1tt for I O channels 5 8 Number of Serial Channels 8 Serial Controller Two ST16C654 Quad UART FIFO 64 byte transmit FIFO 64 byte receive FIFO per channel I O Signals TIP866 10 T1P866 10 ET RS232 and TIP866 11 TIP866 11 ET TTL TxD RTS RxD CTS GND DTR DSR DCD RI additionally for channel 1 and channel 2 TIP866 20 TIP866 20 ET RS422 TxD RxD GND I O Line Termination 1200hms on board between RxD and RxD for TIP866 20 TIP866 20 ET Baud Rates Each channel individually programmable TIP866 10 TIP866 10 ET RS232 up to 115 2 Kbaud TIP866 11 TIP866 11 ET TTL and TIP866 20 TIP866 20 ET RS422 up to 460 8 Kbaud I O Interface Connector 50 conductor flat cable ESD Protection RS232 422 Transmitter TIP866 10 TIP866 10 ET and TIP866 20 TIP866 20 ET 6kV IEC1000 4 2 contact discharge 15kV IEC1000 4 2 air gap discharge RS232 422 Receiver TIP866 10
10. the transmit FIFO or transmit holding register The TxRdy bit of the FIFORDY1 register will be read as 1 after the first character is loaded into the transmit register The corresponding RxR y bit of the FIFORDY1 register will be read as 0 when there is at least 1 character in the receive FIFO The RxR y bit of the FIFORDY1 register will be read as 1 when there are no more characters in the receiver Bit Symbol Description Access Reset Value RXRDY4 RXRDY3 RXRDY2 RXRDY 1 RXRDY channel 1 4 R 1111 TXRDY4 TXRDY3 TXRDY2 TXRDY1 TXRDY channel 1 4 R 0000 Oo INJO AIU OIS Table 4 19 FIFO Ready Status Register 1 FIFORDY1 TIP866 User Manual Issue 1 0 9 Page 19 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 4 2 3 FIFO Ready Status Register 2 Channel 5 8 Offset 0x5F The FIFO Ready Status Register 2 FIFORDY2 is a byte wide read only register It is located within Register Set 1 of Channel 6 FIFORDY2 covers the FIFO status for Quad UART Controller 2 channels 5 8 If a serial channel is in FIFO mode FIFO Control Register bit 0 set to 1 and bit 3 of the FIFO Control Register is set to 1 the corresponding TxRdy bit of the FIFORDY2 register will be read as 1 if the transmit FIFO is completely full It will be read as 0 if one or more transmit FIFO locations are empty Th
11. ABLE 4 4 CHANNEL 2 REGISTER GET 11 TABLE 4 5 CHANNEL 2 REGISTER SET 3 11 TABLE 4 6 CHANNEL 3 REGISTER GET 12 TABLE 4 7 CHANNEL 3 REGISTER SET 3 12 TABLE 4 8 CHANNEL 4 REGISTER GET 13 TABLE 4 9 CHANNEL 4 REGISTER SET 3 13 TABLE 4 10 CHANNEL 5 REGISTER GETT 14 TABLE 4 11 CHANNEL 5 REGISTER SET 3 14 TABLE 4 12 CHANNEL 6 REGISTER SET 1 cccsscccsssssecesssseececssneeceecssneeceessneecesseneecessssaeeeeseneeeessssaeeeeesaes 15 TABLE 4 13 CHANNEL 6 REGISTER SET 3 15 TABLE 4 14 CHANNEL 7 REGISTER GETT 16 TABLE 4 15 CHANNEL 7 REGISTER SET 3 16 TABLE 4 16 CHANNEL 8 REGISTER GETT 17 TABLE 4 17 CHANNEL 8 REGISTER SET 3 17 TABLE 4 18 INTERRUPT VECTOR REGISTER INTVEC cc cccccceccceeeseeeeeecsneeeeecsaeeeeecseeeeeecseeeessneeeeseaes 18 TABLE 4 19 FIFO READY STATUS REGISTER 1 FIFORDY1 ccccccccccsseeeceesseeeeecsneeeeecseeeeesseeeeeeeaes 19 TABLE 4 20 FIFO READY STATUS REGISTER 2 FIFORDY 2 cccccccccccsseeeceesseeeeecsneeeeecseeeeesseeeeseeaes 20 TABLE 5 1 BAUD RATE PROGRAMMING TABLE rrrnnnrrvrrrnnrvrrrrnnrverrrnnvnerrrnnnrerrrrnnnrerrsnnnrerrrnnrnerrsnnrnesrrnnnne 21 TABLE 6 1 PIN ASSIGNMENT I O CONNECTOR TIP866 10 ET RS232 11 GETT 24 TABLE 6 2 PIN ASSIGNMENT I O CONNECTOR TIPoGG20CETIIRGAO 26 TIP866 User Manual Issue 1 0 9 Page 5 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHN
12. EREA EEA 14 4 16 Channel 6 Register SOU EE 15 4 1 6 Channel f Register Set eienen sank nine ENEE firer sura BEE 16 41 8 Channel 8 Register Set isc icccatecicavenevlest seetneeber nase seein shania anes 17 4 2 Special Registers ee ees e EE 18 4 2 1 Interrupt Vector Register Offset ONE 18 4 2 2 FIFO Ready Status Register 1 Channel 1 4 Offset DIE 19 4 2 3 FIFO Ready Status Register 2 Channel 5 8 Offset DND 20 5 BAUD RATE PROGRAMMING sascscsccssccscsstscstscntccnsstetnsnaatnandsccssssdsasseandnassedesssadeaniaane 21 6 PIN ASSIGNMENT UO CONNECTOR nnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnen 23 6 1 50 pin I O connector TIP866 10 ET RS232 11 ET TTL rnnnnnnnnnvnnnnnvnnnnnvnnnnvnnnnnvnnnnnnnnnner 23 6 2 50 pin UO connector TIP866 20 ET RS422 rnnnnnvnvennnnvnnvennnnvnvennnnnnvennnnnnvernnnnnnnernnnnneennnnnnnenr 25 TIP866 User Manual Issue 1 0 9 Page 4 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES List of Figures FIGURE 1 1 BLOCK DIAGRAM anne 6 List of Tables TABLE 2 1 TECHNICAL SPECIFICATION 4 uenige gende EAEE 7 TABLE 3 1 ID PROM CONTENT sene ne e RAA AA 8 TABLE 4 1 I O SPACE ADDRESS MAP vasisciscsecccelsssscdeseassetieesscctelaistcudetonccddeassncdedewssanedesecvessaneeneedsedecencde 9 TABLE 4 2 CHANNEL 1 REGISTER GET 10 TABLE 4 3 CHANNEL 1 REGISTER SET 3 10 T
13. IP866 10 ET Comment Comment RS232 TIP866 10 ET RS232 TIP866 11 ET TTL Signal TIP866 11 ET TTL 36 GND Signal Ground 41 GND Supply for Transition Module 42 5V Supply for Transition Module 49 RI2 Active low 50 DSR2 Active high Active low Table 6 1 Pin Assignment I O Connector TIP866 10 ET RS232 11 ET TTL TIP866 User Manual Issue 1 0 9 Page 24 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 6 2 50 pin UO connector TIP866 20 ET RS422 Pin Signal TIP866 20 ET Comment RS422 1 GND Signal Ground 6 Signal Ground 11 Signal Ground 16 GND Signal Ground 21 GND Signal Ground 26 Signal Ground 31 Signal Ground 36 GND Signal Ground 39 RxD8 RS422 TIP866 User Manual Issue 1 0 9 Page 25 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES Pin Signal TIP866 20 ET Comment RS422 40 RS422 41 Signal Ground 42 50 No connection Table 6 2 Pin Assignment I O Connector TIP866 20 ET RS422 On board signal termination between RxD and RxD is 120 ohms for each channel TIP866 User Manual Issue 1 0 9 Page 26 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A rtisan Artisan Technology Group is your source for qualit
14. LCR set to 0xBF 0x6B Xon 2 Word 8 LCR set to 0xBF 0x6D Xoff 1 Word 8 LCR set to 0xBF Ox6F Xoff 2 Word 8 LCR set to OxBF Table 4 15 Channel 7 Register Set 2 TIP866 User Manual Issue 1 0 9 Page 16 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 4 1 8 Channel 8 Register Set After reset Register Set 1 is selected TEWSS TECHNOLOGIES Register Set 1 is accessible if bit 7 of the Line Control Register LCR Offset 0x77 is set to 0 Offset in Read Mode Write Mode Size Bit IP I O Space 0x71 Receive Holding Register RHR Transmit Holding Register THR 8 0x73 Interrupt Enable Register IER Interrupt Enable Register IER 8 0x75 Interrupt Status Register ISR FIFO Control Register FCR 8 0x77 Line Control Register LCR Line Control Register LCR 8 0x79 Modem Control Register MCR Modem Control Register MCR 8 0x7B Line Status Register LSR 8 0x7D Modem Status Register MSR 8 Ox7F Not used Not used 8 Table 4 16 Channel 8 Register Set 1 Register Set 2 is accessible if bit 7 of the Line Control Register LCR Offset 0x77 is set to 1 The Enhance Feature Register Xon 1 2 and Xoff 1 2 registers are accessible only when LCR is set to OxBF Offset in Read Write Size Bit Comment IP I O Space 0x71 LSB of Divisor Latch DLL 8 LCR bit 7 set to 1
15. OLOGIES 1 Product Description The TIP866 is an IndustryPack compatible module providing eight channels of high performance serial interface Following module options are available e TIP866 10 provides RS232 interface e TIP866 10 ET provides RS232 interface for extended operating temperature e TIP866 11 provides TTL level interface e TIP866 11 ET provides TTL level interface for extended operating temperature e TIP866 20 provides RS422 interface e TIP866 20 ET provides RS422 interface for extended operating temperature Each channel of the modules has a 64 byte transmit FIFO and a 64 byte receive FIFO to significantly reduce the overhead required to provide data to and get data from the transmitters and receivers The FIFO trigger levels are programmable The TIP866 10 ET 11 ET support RxD TxD RTS CTS and GND for each of the eight RS232 TTL channels The TIP866 20 ET support RxD TxD and GND for each of the eight RS422 channels The baud rate is individually programmable for up to 115 2kbaud for the TIP866 10 ET and up to 460 8kbaud for the TIP866 11 ET 20 ET The TIP866 10 ET 20 ET provide ESD protected transceivers up to 15KV according to IEC 1000 4 2 Several transition modules for UO cabling are available e TIP866 TM 10 provides 8 DB25 connectors mounted in a 6U 8TE front panel e TIP866 TM 20 provides 8 RJ45 connectors mounted in a 6U 4TE front panel e TIP866 TM 30 provides 16 4 pin RJ
16. OURCE www artisantg com 4 1 1 Channel 1 Register Set After reset Register Set 1 is selected TEWSS TECHNOLOGIES Register Set 1 is accessible if bit 7 of the Line Control Register LCR Offset 0x07 is set to 0 The special register INTVEC is accessible within this register set Offset in IP Read Mode Write Mode Size Bit I O Space 0x01 Receive Holding Register RHR Transmit Holding Register THR 8 0x03 Interrupt Enable Register IER Interrupt Enable Register IER 8 0x05 Interrupt Status Register ISR FIFO Control Register FCR 8 0x07 Line Control Register LCR Line Control Register LCR 8 0x09 Modem Control Register MCR Modem Control Register MCR 8 0x0B Line Status Register LSR 8 0x0D Modem Status Register MSR 8 OxOF Interrupt Vector Register INTVEC Interrupt Vector Register INTVEC 8 Table 4 2 Channel 1 Register Set 1 Register Set 2 is accessible if bit 7 of the Line Control Register LCR Offset 0x07 is set to 1 The Enhance Feature Register Xon 1 2 and Xoff 1 2 registers are only accessible when the Line Control Register is set to OxBF Offset in Read Write Size Bit Comment IP I O Space 0x01 LSB of Divisor Latch DLL 8 LCR bit 7 set to 1 but OxBF 0x03 MSB of Divisor Latch DLM 8 LCR bit 7 set to 1 but OxBF 0x05 Enhanced Feature Register EFR 8 LCR set to OxBF 0x07 Line Control Reg
17. TIP866 10 ET and TIP866 20 TIP866 20 ET 8kV IEC1000 4 2 contact discharge 15kV IEC1000 4 2 air gap discharge Power Requirements 40mA typical 5V DC no serial channel connected 1mA typical 12V DC no serial channel connected 1mA typical 12V DC no serial channel connected Temperature Range Operating TIP866 xx 0 C to 70 C Operating TIP866 xx ET 40 C to 85 C Storage 40 C to 125 C MTBF TIP866 10 TIP866 10 ET 714778 h TIP866 11 TIP866 11 ET 80904 1h TIP866 20 TIP866 20 ET 667498 h Humidity 5 95 non condensing Table 2 1 Technical Specification TIP866 User Manual Issue 1 0 9 Page 7 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 3 ID Prom Contents Address Function Contents 0x01 ASCII T 0x49 0x03 ASCII P 0x50 0x05 ASCII A 0x41 0x07 ASCII C 0x43 0x09 Manufacturer ID 0xB3 0x0B Model Number 0x1D 0x0D Revision 0x10 OxOF Reserved 0x00 0x11 Driver ID Low Byte 0x00 0x13 Driver ID High Byte 0x00 0x15 Number of bytes used 0x0D 0x17 CRC TIP866 10 ET 0x07 TIP866 11 ET 0x26 TIP866 20 ET OxF8 0x19 TIP866 Board Option TIP866 10 ET OxOA TIP866 11 ET 0x0B TIP866 20 ET 0x14 0x1B Not used 0x00 Ox3F Not used 0x00 Table 3 1 ID PROM Contents
18. VISOR x 1 3x MCR _ Bit7 The baud rate is programmable individually for each channel The divisor value is programmed into the MSB and LSB Divisor Latch Register Register Set 2 of each channel See the note below for programming the MCR Modem Control Register bit 7 After reset for each channel the MCR bit 7 defaults to 1 and the value of the MSB and LSB Divisor Latch Registers results in a divisor value of OxFFFF Baud Rate MCR bit 7 Baud Rate MCR bit 7 Divisor 1 0 DLM DLL 50 200 0x0900 75 300 0x0600 150 600 0x0300 300 1200 0x0180 600 2400 0x00C0 1200 4800 0x0060 2400 9600 0x0030 4800 19 2K 0x0018 7200 28 8K 0x0010 9600 38 4K 0x000C 14 4K 57 6K 0x0008 28 8K 115 2K 0x0004 38 4K 153 6K 0x0003 57 6K 230 4K 0x0002 115 2K 460 8K 0x0001 Table 5 1 Baud Rate Programming Table The highest data rate of the TIP866 10 ET is 115 2Kbaud because of the used RS232 Line Drivers and Receivers For data rates higher than 115 2Kbaud MCR bit 7 must be set to 0 TIP866 11 ET TIP866 20 ET only TIP866 User Manual Issue 1 0 9 Page 21 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES Access to the DLM DLL registers must be enabled in the LCR register These steps should be used to modify the DLM DLL registers e Write 0x80 to LCR register enable access to DLM
19. e corresponding RxRdy bit of the FIFORDY2 register will become 0 when the FIFO trigger level has been reached The RxRdy bit of the FIFORDY2 register will be read as 1 when there are no more characters in the receive FIFO If a serial channel is in FIFO mode FIFO Control Register bit 0 set to 1 and bit 3 of the FIFO Control Register is set to 0 or if the FIFO mode is disabled the TxRdy bit of the FIFORDY2 register will be read as 0 when there are no characters in the transmit FIFO or transmit holding register The TxRdy bit of the FIFORDY2 register will be read as 1 after the first character is loaded into the transmit register The corresponding RxRdy bit of the FIFORDY2 register will be read as 0 when there is at least 1 character in the receive FIFO The RxRdy bit of the FIFORDY2 register will be read as 1 when there are no more characters in the receiver Bit Symbol Description Access Reset Value RXRDY8 RXRDY7 RXRDY6 RXRDY5 RXRDY channel 5 8 R 1111 TXRDY8 TXRDY7 TXRDY6 TXRDY5 TXRDY channel 5 8 R 0000 OoO gt INJO R U ODIS Table 4 20 FIFO Ready Status Register 2 FIFORDY2 TIP866 User Manual Issue 1 0 9 Page 20 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 5 Baud Rate Programming The basic formula of baud rate programming is BaudRate 7 3728MHz 16 x DI
20. ector Register INTVEC Quad UART Controller 1 channels 1 4 generates interrupts on IP interrupt request line INTREQO Quad UART Controller 2 channels 5 8 generates interrupts on IP interrupt request line INTREQ1 TIP866 User Manual Issue 1 0 9 Page 18 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES 4 2 2 FIFO Ready Status Register 1 Channel 1 4 Offset 0x1F The FIFO Ready Status Register 1 FIFORDY1 is a byte wide read only register It is located within Register Set 1 of Channel 2 FIFORDY 1 covers the FIFO status for Quad UART Controller 1 channels 1 4 If a serial channel is in FIFO mode FIFO Control Register bit 0 set to 1 and bit 3 of the FIFO Control Register is set to 1 the corresponding TxRdy bit of the FIFORDY1 register will be read as 1 if the transmit FIFO is completely full It will be read as 0 if one or more transmit FIFO locations are empty The corresponding RxRdy bit of the FIFORDY1 register will become 0 when the FIFO trigger level has been reached The RxRdy bit of the FIFORDY1 register will be read as 1 when there are no more characters in the receive FIFO If a serial channel is in FIFO mode FIFO Control Register bit 0 set to 1 and bit 3 of the FIFO Control Register is set to 0 or if the FIFO mode is disabled the TxRdy bit of the FIFORDY1 register will be read as 0 when there are no characters in
21. ge 15 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 4 1 7 Channel 7 Register Set After reset Register Set 1 is selected TEWSS TECHNOLOGIES Register Set 1 is accessible if bit 7 of the Line Control Register LCR Offset 0x67 is set to 0 Offset in Read Mode Write Mode Size Bit IP I O Space 0x61 Receive Holding Register RHR Transmit Holding Register THR 8 0x63 Interrupt Enable Register IER Interrupt Enable Register IER 8 0x65 Interrupt Status Register ISR FIFO Control Register FCR 8 0x67 Line Control Register LCR Line Control Register LCR 8 0x69 Modem Control Register MCR Modem Control Register MCR 8 0x6B Line Status Register LSR 8 0x6D Modem Status Register MSR 8 Ox6F Not used Not used 8 Table 4 14 Channel 7 Register Set 1 Register Set 2 is accessible if bit 7 of the Line Control Register LCR Offset 0x67 is set to 1 The Enhance Feature Register Xon 1 2 and Xoff 1 2 registers are accessible only when LCR is set to OxBF Offset in Read Write Size Bit Comment IP I O Space 0x61 LSB of Divisor Latch DLL 8 LCR bit 7 set to 1 but OxBF 0x63 MSB of Divisor Latch DLM 8 LCR bit 7 set to 1 but OxBF 0x65 Enhanced Feature Register EFR 8 LCR set to 0xBF 0x67 Line Control Register LCR 8 Always accessible 0x69 Xon 1 Word 8
22. ister LCR 8 Always accessible 0x09 Xon 1 Word 8 LCR set to 0xBF 0x0B Xon 2 Word 8 LCR set to OxBF 0x0D Xoff 1 Word 8 LCR set to OxBF OxOF Xoff 2 Word 8 LCR set to 0xBF Table 4 3 Channel 1 Register Set 2 TIP866 User Manual Issue 1 0 9 Page 10 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 4 1 2 Channel 2 Register Set After reset Register Set 1 is selected TEWSS TECHNOLOGIES Register Set 1 is accessible if bit 7 of the Line Control Register LCR Offset 0x17 is set to 0 The special register FIFORDY1 is accessible within this register set Offset in Read Mode Write Mode Size Bit IP I O Space 0x11 Receive Holding Register RHR Transmit Holding Register THR 8 0x13 Interrupt Enable Register IER Interrupt Enable Register IER 8 0x15 Interrupt Status Register ISR FIFO Control Register FCR 8 0x17 Line Control Register LCR Line Control Register LCR 8 0x19 Modem Control Register MCR Modem Control Register MCR 8 0x1B Line Status Register LSR 8 0x1D Modem Status Register MSR 8 Ox1F FIFORDY1 Register FIFORDY1 Register 8 Table 4 4 Channel 2 Register Set 1 Register Set 2 is accessible if bit 7 of the Line Control Register LCR Offset 0x17 is set to 1 The Enhance Feature Register Xon 1 2 and Xoff 1 2 registers are only accessible when LCR is set
23. san Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES Issue Description Date 1 0 First Issue August 1996 1 1 Revision B December 1996 1 2 Add RS422 Interface December 1996 1 3 I O Pin Assignment December 1997 1 4 General Revision November 2002 1 5 Add Module versions TIP866 xx ET April 2003 1 6 Correction Model Number in chapter ID PROM CONTENTS November 2003 1 7 Baud Rate Programming Note Update December 2003 1 8 New address TEWS LLC September 2006 1 0 9 New Notation for User Manual and Engineering Documentation February 2009 TIP866 User Manual Issue 1 0 9 Page 3 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com TEWSS TECHNOLOGIES Table of Contents 1 PRODUCT DESCRIPTION susen id 6 2 TECHNIGAL ee A e ME 7 gt JD rei Kei e E KC 8 A NP RO DRESSING E 9 4 1 Channel Register SetS mnusvnnnnvvnnnnvnnnnnvnnnnvnnnnvnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 9 4 1 1 Channel Register Set nnsskuansumuneninuujsnmsnijdnitntarbeieadadenmed 10 4 1 2 Channel 2 Register Set 2 euraid rinnan iniaiaiai ARRANA ENANA AANER AEE 11 La Channel 3 Register Sateinen anini RREA AEREA 12 41 4 Channels Register Sat eseon anini shed ARRENE AANA ARAE ENRERE 13 41 5 Channel S Register Set uns enectigee cendenned ising dene AE AAAA
24. ster LCR Offset 0x57 is set to 0 The special register FIFORDY2 is accessible within this register set Offset in Read Mode Write Mode Size Bit IP I O Space 0x51 Receive Holding Register RHR Transmit Holding Register THR 8 0x53 Interrupt Enable Register IER Interrupt Enable Register IER 8 0x55 Interrupt Status Register ISR FIFO Control Register FCR 8 0x57 Line Control Register LCR Line Control Register LCR 8 0x59 Modem Control Register MCR Modem Control Register MCR 8 0x5B Line Status Register LSR 8 0x5D Modem Status Register MSR 8 0x5F FIFORDY2 FIFORDY2 8 Table 4 12 Channel 6 Register Set 1 Register Set 2 is accessible if bit 7 of the Line Control Register LCR Offset 0x57 is set to 1 The Enhance Feature Register Xon 1 2 and Xoff 1 2 registers are accessible only when LCR is set to OxBF Offset in Read Write Size Bit Comment IP I O Space 0x51 LSB of Divisor Latch DLL 8 LCR bit 7 set to 1 but OxBF 0x53 MSB of Divisor Latch DLM 8 LCR bit 7 set to 1 but OxBF 0x55 Enhanced Feature Register EFR 8 LCR set to OxBF 0x57 Line Control Register LCR 8 Always accessible 0x59 Xon 1 Word 8 LCR set to 0xBF 0x5B Xon 2 Word 8 LCR set to 0xBF 0x5D Xoff 1 Word 8 LCR set to OxBF Ox5F Xoff 2 Word 8 LCR set to 0xBF Table 4 13 Channel 6 Register Set 2 TIP866 User Manual Issue 1 0 9 Pa
25. x43 Interrupt Enable Register IER Interrupt Enable Register IER 8 0x45 Interrupt Status Register ISR FIFO Control Register FCR 8 0x47 Line Control Register LCR Line Control Register LCR 8 0x49 Modem Control Register MCR Modem Control Register MCR 8 0x4B Line Status Register LSR 8 0x4D Modem Status Register MSR 8 Ox4F Not used Not used 8 Table 4 10 Channel 5 Register Set 1 Register Set 2 is accessible if bit 7 of the Line Control Register LCR Offset 0x47 is set to 1 The Enhance Feature Register Xon 1 2 and Xoff 1 2 registers are accessible only when LCR is set to OxBF Offset in Read Write Size Bit Comment IP I O Space 0x41 LSB of Divisor Latch DLL 8 LCR bit 7 set to 1 but OxBF 0x43 MSB of Divisor Latch DLM 8 LCR bit 7 set to 1 but OxBF 0x45 Enhanced Feature Register EFR 8 LCR set to OxBF 0x47 Line Control Register LCR 8 Always accessible 0x49 Xon 1 Word 8 LCR set to OxBF 0x4B Xon 2 Word 8 LCR set to OxBF 0x4D Xoff 1 Word 8 LCR set to OxBF Ox4F Xoff 2 Word 8 LCR set to OxBF Table 4 11 Channel 5 Register Set 2 TIP866 User Manual Issue 1 0 9 Page 14 of 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 4 1 6 Channel 6 Register Set After reset Register Set 1 is selected TEWSS TECHNOLOGIES Register Set 1 is accessible if bit 7 of the Line Control Regi
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