(DSPC-8682E) User Guide
Contents
1. 17 3 3 Installation Usage 18 Trusted ePlatform Services AD ANTECH Lob af Advantech Confidential 3 4 DSP Loader DI 19 3 4 1 Query DSP Information 19 3 4 2 Download DSP Program Image 20 3 4 3 DSP Memory Read uoce 21 3 4 4 DSP Memory 22 3 4 5 Download DSP Binary File 22 3 4 6 Save DSP Memory as a Binary File 23 3 4 7 DSP Local c r em 24 4 Reference In qiu Me 25 4 1 Patch of Platform Library and Library 25 4 1 1 How to Use Patch and Pre built 25 4 1 2 Build 1 e 25 4 2 DSP DDRS 1 742 ec SN HM PUR MIR 27 4 2 1 Ed 28 4 2 2 Usagre P 28 4 3 DSP Local e 29 4 3 1 Build 29 4 3 2 30 4 4 Ethernet and Simple Web 30 4 4 12. Configuration Completed 4 5 3 PC Site Utility The PC site demo application dsp_demo contains two commands demo and console function Trusted ePlatform Services AD ANTECH TA Advantech Confidential 4 5 3 1 Inter Communication The demo command is used to demonstrate the negotiation between DSP and PC host dsp demo will perform the data blocks read write and wait the interrupt signal which is sent from PCle driver The command syntax is dsp demo demo chip chip the number of DSPs parameter selects which DSP will be accessed by 4 5 3 2 Console Simulation This command is for creating a virtual console to display the debug message by the program running in specific DSP chip from DSP 0 to DSP 7 and cores core from CPU core 0 to CPU 7 The command syntax is dsp demo console chip core The following example displays the debug message of demo evm6678l hex DSP demo program which is executed by CPU 0 in DSP 0 Lightning PCIE examples ipc pc bin dsp demo console 0 0 Synchronizing done PCIe Hello World Example this is DSPO Debug GEM INTC Configuration Completed Debug Configuration Debug 0 Configuration Completed DSPO generated interrupt to host DSPO receive MSI interrupt from host DSPO finish operating dummy data Note DSP program demo evm6678l hex should be downloaded to DSP device first before issuing this virtual console
3. RP n 30 4 4 2 Usager 31 4 5 Communication between 33 4 5 1 Build TE 33 4 5 2 Bro eect 34 4 5 3 Site Utility 35 Trusted ePlatform Services ADMNTECH soe 6 Advantech Confidential 4 5 4 DSP Demo 36 4 5 5 IPC Demo on SYS BIOS DSP 38 4 6 Image Processing Demonstration 39 4 6 1 Build TAS WUC T 40 4 6 2 2 40 Trusted ePlatform Services Advantech Confidential 1 Introduction This document describes how to set up the software configurations for Octal DSP PCle board DSPC8682E before using it The DSPC8682E contains eight Texas Instruments TMS320C6678 DSPs with PCle HyperLink Serial RapidlO and SGMII interfaces 1 1 Hardware Description The placement of the DSPC8682E is shown in Figure 1 1 Each board contains eight TMS320C6678 codename Shannon DSPs one PLX PEX8748 PCle switch and one Xilinx XC3S200AN FPGA The TMS320C6678 multi core fixed and floating point digital signal processor is based on advanced KeyStone architecture from Texas Instruments
4. ddr3 evmc66781 bin DSPC8682E init out gt text _c_int00 _ ddr3 evmc66781 bin DSPC8682E init out gt text ddr3 evmc66781 bin DSPC8682bE init out gt const ddr3 evmc66781 bin DSPC8682E init out gt cinit DSP type silicon Version PG2 0 DSP maximum frquency limit 1GHz Load HEX image bin DSPC8682E init hex to 0 0 start address 0x00830000 Load HEX OK Trusted ePlatform Services AD ANTECH Advantech Confidential DSP type silicon Version PG2 0 DSP maximum frquency limit 1GHz Load HEX image bin DSPC8682E init hex to 1 0 start address 0x00830000 Load HEX OK DSP type silicon Version PG2 0 DSP maximum frquency limit 1GHz Load HEX image bin DSPC8682E init hex to 2 0 start address 0x00830000 Load HEX OK DSP type silicon Version PG2 0 DSP maximum frquency limit 1GHz Load HEX image bin DSPC8682E init hex to 3 0 start address 0x00830000 Load HEX OK DSP type silicon Version PG2 0 DSP maximum frquency limit 1GHz Load HEX image bin DSPC8682E init hex to 4 0 start address 0x00830000 Load HEX OK DSP type silicon Version PG2 0 DSP maximum frquency limit 1GHz Load HEX image bin DSPC8682E init hex to 5 0 start address 0x00830000 Load HEX OK DSP type silicon Version PG2 0 DSP maximum frquency limit 1GHz Load HEX image bin DSPC8682E init hex to 6 0 start address 0x00830000 Load HEX OK DSP type
5. 6 1 2 DSPG 8582E Block Diagram icio itane 6 1 3 pica guis Edah 7 1 4 8 1 5 HyperLink Interface erret 8 1 6 Serial RapidlO Inter ace eects 8 1 7 6 esac 9 1 8 DSP ATOM 9 1 9 Hardware Environment Setting Lennon repetit nri erre etit tk b eerte opu ERE 10 2 Pee eee 13 2 1 API Interface of DSP 13 2 2 DSP Program Loader Utility rer Rs Ee ERE Ex RES 14 2 3 Example DDR3 TRIBSIIZSUOLE sicca 14 2 4 Example DSP Initialization for Local 15 2 9 Example Simple Web Server RUE 15 2 6 Example PC DSP Communication cesses 15 2 7 Example Image Processing 15 2 8 Patch Platform Library and 222 15 3 DSP Progr m MED E UE 17 3 1 Host System 17 3 2 Build 17 3 2 1 Build the Driver and Demo
6. home advantech test image output jpg Save Binary file home advantech test image output jpg from DSP 1 start address 0x80000000 Size 0x007261e9 Saved from dsp 7496169 bytes Time measured 21871 us Save Binary OK Trusted ePlatform Services AD ANTECH Advantech Confidential 3 4 7 DSP Local Reset The command syntax is dsp loader reset chip The command is to do a local reset of DSP The detailed description of each parameter is shown below 1 chip the chip are the number of DSPs attached to the PC The following example reset 5 0 Lightning PCIE dsp loader app bin dsp loader reset 0 Iterations waited for entry point to clear 1 Dsp 0 DSP Reset success Trusted ePlatform Services AD ANTECH Advantech Confidential 4 Reference Implementations 4 1 Patch of Platform Library and NDK Library The example programs have to link with DSPC8682 platform library and NDK library A developer has to install MCSDK first and applies the provided patch The default path of MCSDK in Windows is C Program Files Texas Instruments or 4 1 1 How to Use Patch and Pre built Libraries 1 Copy Lightning _PCIE patch pdk_C6678_ 1 1 2 5 2 Paste to C Program Files Texas Instruments pdk_C6678_1_1 2 5 3 The pre built libraries are included in the provided patch a developer can use these libraries directly 4 1 2 Build Instruction Steps to build platform lib are listed below 1 Impo
7. 1 1 0 0 7 1 1 1 Table 1 2 DSP ID and GPIO table Trusted ePlatform Services AD ANTECH Advantech Confidential The Linux command lspci can list which type of board it is running by checking subsystem ID and subsystem vendor ID as table 1 3 SUBSYS ID SUBSYS VEN ID Value 0x8682 Table 1 3 Subsystem ID and vendor ID table 15 vvnn d b005 04 00 0 Multimedia controller 0480 Texas Instruments Device 104c b005 01 Subsystem Advantech Co Ltd Device 13fe 8682 Control I O Mem BusMaster SpecCycle MemWINV VGASnoop ParErr Stepping SERR FastB2B DisINTx Status Cap 66MHz UDF FastB2B ParErr DEVSEL fast gt TAbort lt TAbort lt MAbort gt SERR lt PERR INTx Latency 0 Cache Line Size 64 bytes Interrupt pin A routed to IRQ 11 Region 0 Memory at f8800000 32 bit non prefetchable size 4K Region 1 Memory at df000000 32 bit prefetchable size 16M Region 2 Memory at de000000 32 bit prefetchable size 16M Region 3 Memory at dc000000 32 bit prefetchable size 32M Region 4 Memory at d8000000 32 bit prefetchable size 64M Capabilities lt access denied gt 1 9 Hardware Environment Setting The DSPC8682E supports two boot modes Emulation mode and 2 mode The user select boot mode by Switch 1 which is shown in Figure 1 4 The Emulation mode is mainly for JTAG debug The 2 boot mode is usually
8. Each TMS320C6678 on DSPC8682E is supported by external DDR3 the DDR3 module type depends on different HW version devices for data and program storage The eight TMS320C6678 devices are connected through PEX8748 PCle device which is 48 lane 12 port PCle Gen3 switch The XC3S200AN FPGA device provides the required control signals to the DSPC8682E 12Vdc Power 10A PLX PEX8748 PCIEx8 Gen3 PCB Full Size 312x111 15mm Figure 1 1 DSPC 8682E Placement 1 2 DSPC 8682E Block Diagram An interface block diagram for the DSPC8682E is shown in Figure 1 2 Each TMS320C6678 DSP contains several interfaces such as DDR HyperLink Serial RapidlO and SGMII Trusted ePlatform Services AD ANTECH T Advantech Confidential Broadcom BCM5482S DSP5 Block TMS320C6678 TMS320C6678 TMS320 6678 Ei Gen3 Figure 1 2 DSPC 8682E Interface Block Diagram 1 3 DDR3 Interface Each TMS320C6678 DSP is connected to four 4Gbit DDR3 memory devices with 64 bit data and 2GB capacity at current implementation The DDR memory space is ranging from 0x80000000 to OxFFFFFFFF at DSP device Note The A101 version board is mounted 2Gbit DDR3 memory devices and 1GB capacity The DDR memory space of those bo
9. Existing CCS CCE Eclipse Projects 2 Select DSPC8682E as active configuration Clean the demo_evmc6678l_init project and re build the project After build is completed init out and init map will be generated under Lightning_PCIE examples ddr3 evmc6678l bin DSPC8682E directory 4 2 2 Usage User can use the shell script examples script DSPC8682E init_1000 sh or init_1250 sh to initialize DSP DDR the procedure is composed of three jobs 1 Convert out to hex by executable Hex6x 2 Externally set PLL Multiplier configuration by dsp_loader 3 Load hex to DSP by dsp_loader There are two scripts init_1000 sh and init_1250 sh for users to initialize DSP They load the init hex in Lightning_PCIE bin DSP initialization can be done by invoking the init scripts The difference between init_1000 sh and init_1250 sh is that the former runs DSP at 1GHz the latter overclocks DSP to 1 25GHz There is the prebuilt binary bundled in Lightning_PCIE bin Users can initialize DSP DDR module without building the image from source However when running the script it will show the version of your DSP PG1 or PG2 and for PG2 chip it will also show the maximum running frequency e g 1GHz 1 2GHz 1 25GHz Notice At present we only guarantee the stability for PG2 version of C6678 to run at 1GHz The following example initializes 4 DSP Lightning_PCIE examples script DSPC8682E init_1000 sh 8 Translating to Intel format
10. and sRIO ID table Trusted ePlatform Services TEC Advantech Confidential 1 7 SGMII Interface TMS320C6678 DSP contains an on chip Ethernet switch with two Ethernet interfaces EMACO and EMAC1 TMS320C6678 DSP can connect to another DSP by Ethernet interface without extra Ethernet switch in between The SGMII interface connection and the topology of the Ethernet link on the DSPC8682E is shown in Figure 1 2 The DSPO on DSPC8682bE contains two SGMII interfaces and EMACO is connected to Broadcom BCM5482S Ethernet PHY for external Ethernet access and EMAC1 is connected to EMACO of DSP1 EMAC1 of is connected to EMACO of DSP2 EMAC1 of DSP2 is connecting to EMACO of DSP3 EMAC1 of DSP3 is connecting to EMACO of DSP4 EMAC1 of DSP4 is connecting to EMACO of DSP5 EMAC1 of DSP5 is connecting to EMACO of DSP6 The DSP7 is connected to Broadcom 54825 Ethernet PHY for external Ethernet access and EMACO is connected to EMAC1 of DSP6 Programmers only need to enable Ethernet switch feature of TMS320C6678 DSP and Ethernet packet will forward to the matched DSP by hardware accelerator of on chip Ethernet switch without intervention of DSP cores inside 1 8 DSP Identification The DSPC8682E use GPIO 1 3 pins to identify each DSP and the assignment of DSP ID is shown below GPIO2 1 DSPO 0 0 0 0 1 0 0 1 DSP2 0 1 0 DSPS3 0 1 1 0 4 1 0 0 DSP5 1 0 1 DSP6
11. command Refer to the source code of DSP demo program to get detailed implementation 4 5 4 DSP Demo Program DSP demo program configures DSP CSL INTC registers to receive PCle Legacy INTB and MSIO interrupt from PC host The procedure of demo example is illustrated below with flow chart displayed in Figure 4 6 1 DSP application set up INTC for ISR handler to receive Legacy INTB and MSIO then wait the interrupt sent from PC host Trusted ePlatform Services AD ANTECH T Advantech Confidential 2 PC host writes test data pattern whose length is 640 byte to DSP DDR and sends interrupt to DSP after finishing the writing of the test data pattern 3 The test data pattern in DDR will be added by 1 when DSP receives the interrupt from PC host After finishing the operation DSP will send an interrupt back to PC host 4 PC Host receives the interrupt from DSP as the indication that the test data pattern has already been changed and prints the test data pattern 5 Repeat the communication 1000 times dsp loader starts DSP IPC demo starts PCIE boot mode complete enter IDLE Write Dummy to DSP DDR MAX DEMO TRI Increment each DWORD in DDR Interrupt Set DSP MSIO Print Dummy dsp_loader enas Figure 4 6 Flow Diagram of IPC Example Besides the interrupt demo the demo code also contains the virtua
12. directory Trusted ePlatform Services AD ANTECH Advantech Confidential 4 4 2 Usage User can use the shell script Lightning PCIE examples scrip DSPC8682E ethernet sh to setup Ethernet program on each DSP automatically The following steps set up ethernet program on 8 DSPs 1 Perform the init 1000 sh to initialize DDR 2 Perform the ethernet sh to convert client evmc6678l out to client evmc6678l hex and load the hex file into each DSP Lightning PCIE examples script DSPC8682E ethetnet sh 8 Translating to Intel format f web client evmc66781 DSPC8682bE client evmc66781 0out gt text c 1 100 web client evmc66781 DSPC8682bE client evmc66781 out gt f web client evmc66781 DSPC8682bE client evnc66781 out gt const f web client evmc66781 DSPC8682bE client evnc66781 0out gt Switch 1 web client evmc66781 DSPC8682bE client evmc66781 out gt vecs Lf web client evmc66781 DSPC8682bE client evmc66781 0out gt Switch 2 web client evmc66781 DSPC8682E client_evmc66781 out gt Load HEX image bin DSPC8682E client_evmc66781 hex to 0 0 start address 0x80300000 Load HEX OK Load HEX image bin DSPC8682E client_evmc66781 hex to 1 0 start address 0x80300000 Load HEX OK Load HEX image bin DSPC8682E client_evmc66781 hex to 2 0 start address 0x80300000 Load HEX OK Load HEX image bin DSPC8682E client
13. of each parameter is shown below 1 chip the chip are the number of DSPs attached to the PC 2 address read data address The following example is to read DSP 2 data at address 0x10800000 Lightning_PCIE dsp_loader app bin dsp_loader rmem 2 0 10800000 0x01bc54f6 3 4 4 DSP Memory Write The command syntax is dsp_loader load chip address value The command is to write a 32bits DWORD into DSP memory The detailed description of each parameter is shown below 1 chip the chip are the number of DSPs attached to the PC 2 address written data address 3 value written data The following example writes data Ox55AA55AA into DSP 2 at address 0x10800000 Lightning_PCIE dsp_loader app bin dsp_loader 2 0x10800000 0x55aa55aa Lightning_PCIE dsp_loader app bin dsp_loader rmem 2 0 10800000 Ox55aa55aa 3 4 5 Download DSP Binary File The command syntax is dsp loader loadbinary chip address size transfer type bin file name The command is to write a bin file into DSP memory The detailed description of each parameter is shown below 1 chip the chip are the number of DSPs attached to the PC 2 address written data address 3 size written data size O for all data of file 4 transfer type 0 for CPU memopy 1 for DMA Trusted ePlatform Services AD ANTECH T Advantech Confidential 5 bin file name bin file name is the full path of binary file name which is loa
14. selected by Switch 1 DSPC 8682E includes eight 126 EEPROMSs to support the TMS320C6678 DSPs and each 2 EEPROM contains program for 2 stage boot loader The 2 stage boot loader will configure PLL and PCIE BAR window when DSP boots up from 12 EEPROM Table 1 4 and Table 1 5 show the detailed configuration of Switch 1 Trusted ePlatform Services AD ANTECH Advantech Confidential Figure 1 4 I2C Boot Mode PCIE boot Setting Switch 1 pins 4 3 2 1 Table 1 4 Switch 1 pin decoding Bit Field Value Description 4 2 111 Emulation boot mode 110 2 boot mode Boot from address 0x51 32bits address BAR setting 100 2 boot mode Boot from address 0x50 64bits address BAR setting Others Reserved 1 Endian 0 Little endian 1 Big endian Table 1 5 Switch 1 Configuration Bit Field Description The Figure 1 5 DIP switch is used to setup sRIO switch mode as below table Trusted ePlatform Services AD ANTECH TM Advantech Confidential Value Description SRIO switch in 2x mode QCFG pins 0 7 201010101 SRIO switch in 1x mode QCFG pins 0 7 21 1111111 0000 1111 Table 1 6 CPS 1616 sRIO switch mode setting Figure 1 5 4 pins DIP switch to setup IDT 1616 switch mode CAUSION It is a known issue when DSPC 8682E boots through secondary boot loader by 2 boot mode the DSP may not complete
15. to get detailed procedure of the DSP demo program Lightning_PCIE examples script DSPC8682E ipc sh 1 Translating to Intel format ipc dsp evmc66781 bin DSPC8682E demo evm66781 out gt text int0O ipc dsp evmc66781 bin DSPC8682bE demo evn66781 o0ut gt text ipc dsp evmc66781 bin DSPC8682bE demo evm66781 o0ut gt const ipc dsp evmc66781 bin DSPC8682E demo evm66781 out gt csl ipc dsp evmc66781 bin DSPC8682bE demo evm66781 out gt switch ipc dsp evmc66781 bin DSPC8682bE demo evm66781 out gt cinit Load HEX image bin DSPC8682E demo_evm66781 hex to 1 0 start address 0x00840000 Load HEX OK DDR of DSP is initialized ready to write dummy data to DSP dump dummy buffer before DSP operation 0x607180 0x6071a0 0 6071 0 0 6071 0 0 607200 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000008 00000009 0000000 00000006 0000000 0000000d 0000000e 0000000f 00000010 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018 00000019 0000001a 0000001b 0000001c 0000001d 0000001e 0000001f 00000020 00000021 00000022 00000023 00000024 00000025 00000026 00000027 Trusted ePlatform Services AD ANTECH Advantech Confidential 0x607220 00000028 00000029 0000002 0000002b 0000002c 0000002d 0000002 0000002f 0x607240 00000030 00000031 00000032 00000033 00000034 00000035 00000036 00000037 0x607260 0
16. 0 0000 04 00 TI667X registers mapped to Oxffffc9000035e000 Major 249 Minor 1 assigned Added device to the sys file system BAR Configuration pci 0000 04 00 Start Length Flags pci 0000 04 00 Oxfb8ff000 00004096 0 00040200 pci 0000 04 00 0 000000 16777216 0 00042208 pci 0000 04 00 0xae000000 16777216 0 00042208 pci 0000 04 00 0 000000 33554432 0 00042208 pci 0000 04 00 0000 05 00 pci 0000 05 00 pci 0000 05 00 TI667X registers mapped to Oxffffc9000037e000 Major 249 Minor 2 assigned Added device to the sys file system BAR Configuration pci 0000 05 00 Start Length Flags pci 0000 05 00 Oxfb9ff000 00004096 0 00040200 0000 05 00 0xb7000000 16777216 0 00042208 1 0000 05 00 0xb6000000 16777216 0 00042208 pci 0000 05 00 0xb4000000 33554432 0 00042208 pci 0000 05 00 pci 0000 06 00 pci 0000 06 00 pci 0000 06 00 pci 0000 06 00 TI667X registers mapped to Oxffffc9001097e000 Major 249 Minor 3 assigned Added device to the sys file system BAR Configuration Start Length Flags Trusted ePlatform Services AD ANTECH Advantech Confidential pci 0000 06 00 0 Oxfbaff000 00004096 0 00040200 0000 06 00 0 Oxbf000000 16777216 0 00042208 pci 0000 06 00 0 0 000000 16777216 0 00042208 1 0000 06 00 0 Oxbc000000 33554432 0 00042208 pci 0000 06 00 0 TI667X re
17. 0 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave hex to 5 5 hex to 5 hex to 5 hex to 6 hex to 6 hex to 6 hex to 6 hex to 6 hex to 6 hex to 6 hex to 7 hex to 7 to 7 hex hex to 7 Trusted ePlatform Services AD ANTECH Advantech Confidential start address 0x0c100000 Load HEX OK Load HEX image bin DSPC8682E image_processing_evmc66781_slave hex to 7 5 start address 0x0c100000 Load HEX OK Load HEX image bin DSPC8682E image_processing_evmc66781_slave hex to 7 6 start address 0x0c100000 Load HEX OK Load HEX image bin DSPC8682E image_processing_evmc66781_slave hex to 7 7 start address 0x0c100000 Load HEX OK Load HEX image bin DSPC8682bE image processing evmc66781 master hex to 0 0 start address 0x0c000000 Load HEX OK Load HEX image bin DSPC8682bE image processing evmc66781 master hex to 1 0 start address 0x0c000000 Load HEX OK Load HEX image bin DSPC8682bE image p
18. 0000020 0x607200 00000021 00000022 00000023 00000024 00000025 00000026 00000027 00000028 0x607220 00000029 0000002a 0000002b 0000002c 0000002d 0000002e 0000002f 00000030 0x607240 00000031 00000032 00000033 00000034 00000035 00000036 00000037 00000038 0x607260 00000039 0000003a 0000003b 0000003c 0000003d 0000003e 0000003f 00000040 0x607280 00000041 00000042 00000043 00000044 00000045 00000046 00000047 00000048 0 6072 0 00000049 0000004 00000046 0000004 00000044 0000004 0000004 00000050 0 6072 0 00000051 00000052 00000053 00000054 00000055 00000056 00000057 00000058 0 6072 0 00000059 0000005 00000056 0000005 00000054 0000005 0000005f 00000060 0 607300 00000061 00000062 00000063 00000064 00000065 00000066 00000067 00000068 0 607320 00000069 0000006 00000066 0000006c 00000064 0000006 0000006f 00000070 0 607340 00000071 00000072 00000073 00000074 00000075 00000076 00000077 00000078 0 607360 00000079 0000007 00000076 0000007 00000074 0000007e 0000007f 00000080 0 607380 00000081 00000082 00000083 00000084 00000085 00000086 00000087 00000088 0x6073a0 00000089 0000008a 0000008b 0000008c 0000008d 0000008e 0000008f 00000090 0x6073c0 00000091 00000092 00000093 00000094 00000095 00000096 00000097 00000098 0x6073e0 00000099 0000009a 0000009b 0000009c 00000094 0000009e 0000009f 000000a0 Synchronizing done PCIe Hello World Example this is 05 1 Debug GEM INTC Configuration Completed Debug Configuration Debug
19. 0000038 00000039 0000003a 0000003b 0000003c 0000003d 0000003e 0000003f 0x607280 00000040 00000041 00000042 00000043 00000044 00000045 00000046 00000047 0x6072a0 00000048 00000049 0000004a 0000004b 0000004c 0000004d 0000004e 0000004f 0x6072c0 00000050 00000051 00000052 00000053 00000054 00000055 00000056 00000057 0x6072e0 00000058 00000059 0000005a 0000005b 0000005c 0000005d 0000005e 0000005f 0x607300 00000060 00000061 00000062 00000063 00000064 00000065 00000066 00000067 0x607320 00000068 00000069 0000006a 0000006b 0000006c 0000006d 0000006e 0000006f 0x607340 00000070 00000071 00000072 00000073 00000074 00000075 00000076 00000077 0x607360 00000078 00000079 0000007a 0000007b 0000007c 0000007d 0000007e 0000007f 0x607380 00000080 00000081 00000082 00000083 00000084 00000085 00000086 00000087 0x6073a0 00000088 00000089 0000008 0000008b 0000008c 0000008d 0000008e 0000008f 0x6073c0 00000090 00000091 00000092 00000093 00000094 00000095 00000096 00000097 0x6073e0 00000098 00000099 0000009 0000009b 0000009 0000009d 0000009e 0000009 receive interrupt from dsp1 dummy data has already been changed by DSP dump dummy_buffer after DSP operation 0x607180 00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000008 0x6071a0 00000009 0000000 0000000b 0000000c 0000000d 0000000e 0000000f 00000010 0 6071 0 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018 0 6071 0 00000019 0000001a 00000016 0000001c 0000001d 0000001e 0000001f 0
20. 00006 00000070 0x607340 00000071 00000072 00000073 00000074 00000075 00000076 00000077 00000078 0x607360 00000079 0000007 0000007b 0000007c 0000007d 0000007 0000007 00000080 0x607380 00000081 00000082 00000083 00000084 00000085 00000086 00000087 00000088 0x6073a0 00000089 0000008a 00000086 0000008c 00000084 0000008 0000008 00000090 0x6073c0 00000091 00000092 00000093 00000094 00000095 00000096 00000097 00000098 0x6073e0 00000099 0000009 0000009b 0000009c 00000094 0000009 0000009 000000a0 4 6 Image Processing Demonstration The image processing program is modified from the example codes MCSDK This application shows implementation of an image processing system using a simple multicore framework This application will run Tl image processing kernels imagelib on multiple cores to do image processing eg edge detection etc on an input image Slave Processing Node s Core 0 SYS BIOS Master Processing Node Core 1 NDK DHCP HTTP 8YS BIOS 8YSIBIOS Core N 373 905 Figure 4 7 Image Processing Application Software Framework The user input image will be BMP image The image will be transferred to external memory using http The Ethernet port on the bracket of the DSPC8682E must be connected to an external Ethernet switch support gigabit rates before running this example Each DSP Trusted ePlatform Services AD ANTECH Advantech Confidential has a fix
21. 1 Host System Requirement A reference of the OS used to develop and execute this software release is 1 Linux distribution Ubuntu 10 10 Other distributions including Debian Redhat CentOS and Fedora should work with this software package 2 Kernel Linux kernel version 2 6 35 22 In fact the driver should work with any kernel with version gt 2 6 20 3 Pre required Library libreadline5 dev deb or libreadline5 dev rpm for Redhat families 4 DSP development tool Code Composer Studio v5 1 or higher MCSDK for TMS320C66x Processors V2 01 02 05 please refer to web site http software dl ti com sdoemb sdoemb public sw bios mcsdk 02 01 02 05 DS html 3 2 Build Instruction 3 2 1 Build the Driver and Demo Application The driver is closely tied to Linux kernel running on PC therefore it must be rebuilt to work with the supporting kernel The commands for building PCIE driver are listed below Lightning_PCIE make clean Lightning PCIE make This compiles the PCle kernel driver user mode driver dsp loader utility and pc site application of ipc example The Module libraries can be found the dsp_loader driver module directory The user mode driver library will be generated in the dsp_loader driver lib directory The dsp loader executable can be found dsp_loader app bin directory The pc site application dsp_demo executable will be produced in the examples ipc pc bin Trusted ePlatform Ser
22. 100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 hex hex hex hex hex hex hex hex hex hex hex hex hex to 3 to 3 to 4 to 4 to 4 to 4 to 4 to 4 to 4 to 5 to 5 to 5 to 5 6 Trusted ePlatform Services AD ANTECH Advantech Confidential image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c10000
23. 8f 0x6073c0 00000090 00000091 00000092 00000093 00000094 00000095 00000096 00000097 0x6073e0 00000098 00000099 0000009 0000009b 0000009 0000009d 0000009 0000009 receive interrupt from dsp1 dummy data has already been changed by DSP dump dummy_buffer after DSP operation 0x607180 00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000008 0x6071a0 00000009 0000000 00000006 0000000c 00000004 0000000 0000000 00000010 Trusted ePlatform Services AD ANTECH Advantech Confidential 0x6071c0 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018 0x6071e0 00000019 0000001a 0000001b 0000001 0000001d 0000001e 0000001 00000020 0x607200 00000021 00000022 00000023 00000024 00000025 00000026 00000027 00000028 0x607220 00000029 0000002 0000002b 0000002c 00000024 0000002e 0000002 00000030 0x607240 00000031 00000032 00000033 00000034 00000035 00000036 00000037 00000038 0x607260 00000039 0000003a 0000003b 0000003c 0000003d 0000003e 0000003 00000040 0x607280 00000041 00000042 00000043 00000044 00000045 00000046 00000047 00000048 0x6072a0 00000049 0000004 0000004b 0000004c 0000004d 0000004 0000004 00000050 0x6072c0 00000051 00000052 00000053 00000054 00000055 00000056 00000057 00000058 0x6072e0 00000059 0000005 00000056 0000005c 0000005d 0000005 0000005 00000060 0x607300 00000061 00000062 00000063 00000064 00000065 00000066 00000067 00000068 0x607320 00000069 0000006 00000066 0000006c 00000064 0000006 00
24. DSP operation 0x607180 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 0x6071a0 00000008 00000009 0000000 00000006 0000000c 0000000d 0000000 0000000f 0x6071c0 00000010 00000011 00000012 00000013 00000014 00000015 00000016 00000017 0x6071e0 00000018 00000019 0000001 0000001b 0000001c 0000001d 0000001 0000001f 0x607200 00000020 00000021 00000022 00000023 00000024 00000025 00000026 00000027 0x607220 00000028 00000029 0000002 0000002b 0000002 0000002d 0000002e 0000002 0x607240 00000030 00000031 00000032 00000033 00000034 00000035 00000036 00000037 0x607260 00000038 00000039 0000003a 0000003b 0000003c 0000003d 0000003 0000003 0x607280 00000040 00000041 00000042 00000043 00000044 00000045 00000046 00000047 0x6072a0 00000048 00000049 0000004a 0000004b 0000004c 0000004d 0000004 0000004f 0x6072c0 00000050 00000051 00000052 00000053 00000054 00000055 00000056 00000057 0x6072e0 00000058 00000059 0000005a 0000005b 0000005c 0000005d 0000005e 0000005f 0x607300 00000060 00000061 00000062 00000063 00000064 00000065 00000066 00000067 0x607320 00000068 00000069 0000006a 0000006b 0000006c 0000006d 0000006e 0000006f 0x607340 00000070 00000071 00000072 00000073 00000074 00000075 00000076 00000077 0x607360 00000078 00000079 0000007a 0000007b 0000007c 0000007d 0000007e 0000007f 0x607380 00000080 00000081 00000082 00000083 00000084 00000085 00000086 00000087 0x6073a0 00000088 00000089 0000008 0000008b 0000008c 0000008d 0000008 000000
25. K Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682E image processing 781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682E image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c
26. Trusted ePlatform Services AD ANTECH Advantech Confidential DSPC 8682E User Guide Revision v0 7 Holland Huang Job Supervisor Signature Initiated by Joey Shih Title Engineer Dick Lin Job Software Manager Signature Approved Title by Job Signature Title Approved Release Release Date Status Trusted ePlatform Services AD ANTECH alae Advantech Confidential Revision History Version Date Author Description 0 1 06 19 12 Holland Huang Initial draft Joey Shih 0 6 11 16 12 Holland Huang 4 The version number of this document is changed to synchronize with SW package 0 6 2 The SW package 0 6 support Samsung 4G DDR module 3 Add subsystem ID and subsystem vendor ID 4 Add boot from address 0x50 to support 64bits address BAR 5 Add IDT CPS 1616 5 switch mode configuration Joey Shih 0 7 04 03 13 Holland Huang 1 The SW package 0 7 support MCSDK version 2 01 02 05 2 Add individual platform library for DSPC8681 and DSPC8682 in patch of MCSDK 3 Add user mode PCle driver and DSP local reset function 4 Add DSP init script to support DSP running at 1GHz and 1 25GHz 5 IPC example modification and support PCle interrupt in DSP SYS BIOS application Trusted ePlatform Services AD ANTECH P Advantech Confidential Content T sooo dii tme 6 1 1 Hardware Description Me
27. _evmc66781 hex to 3 0 start address 0x80300000 Load HEX OK Load HEX image bin DSPC8682E client_evmc66781 hex to 4 0 start address 0x80300000 Load HEX OK Load HEX image bin DSPC8682E client_evmc66781 hex to 5 0 start address 0x80300000 Load HEX OK Load HEX image bin DSPC8682E client_evmc66781 hex to 6 0 start address 0x80300000 Load HEX OK Load HEX image bin DSPC8682E client_evmc66781 hex to 7 0 start address 0x80300000 Load HEX OK Trusted ePlatform Services AD ANTECH TC Advantech Confidential 3 Check the result by internet browser The URL of DSPs are http 192 168 1 10X X 1 8 The result is shown in Figure 4 4 and Figure 4 5 Eek eF X Yahoo Seas Client Demo Windows Internet Explorer GO E 192 168 1 108 dx SEO HAV RAA A 1 BSHD E ho IRO dp Client Demo TEXAS INSTRUMENTS TCP IP Sample Client Program This page demonstrates how TCP IP can be used to interface your DSP application to a standard WEB browser View real time TCP IP stack statistics Display IP Address Information O Display Sockets Usage ODisplay Route Table Display Selected This this a small example page being served out of a RAM file system It uses CGI functions on the DSP to dynamically create HTML WEB pages The form to the right use
28. ards will be ranging from 0x80000000 to OXBFFFFFFF at DSP device User can distinguish the HW version on DSPC 8682E backside 19C2868200 is A101 19C2868201 01 is A102 Trusted ePlatform Services AD ANTECH Advantech Confidential Figure 1 3 Bar Code Label of DSPC 8682E 1 4 PCle Interface Each TMS320C6678 DSP is connected to PEX8748 switch by x2 lane of PCle Gen3 with 5Gb speed per lane The PEX8748 PCle switch will connect the DSPC8682E to host PC through x8 lane interface 1 5 HyperLink Interface Each pair of TMS320C6678 DSP devices are connected by eight lanes of HyperLink interface with 50Gbaud rate in between DSPO and DSP7 is the first DSP pair DSP1 and DSP6 is the second DSP pair DSP2 and DSP5 is the third DSP pair and DSP3 and DSP4 is the fourth DSP pair Each DSP pair can exchange data to link partner via HyperLlink interface as well 1 6 Serial RapidlO Interface The DSPC8682E has two ways to communicate to the other DSPs through Serial RapidlO sRIO at 5G baud rate Each TMS320C6678 DSP can use sRIO 0 and porti to exchange packets with the other DSPs directly in 1x mode or through IDT CPS1616 sRIO switch by port2 to communicate to the other DSPs in 2x mode The CPS 1616 sRIO switch uses SRIO ID of packets to determine the data flow routing path The DSP ID and sRIO ID is show below table DSP ID sRIO ID 0 7 1 8 2 4 3 3 4 6 5 5 6 2 7 1 Table 1 1 DSP ID
29. b lib debug 4 Repeat step 2 and step 3 select Debug as active configuration and re build the project ti platform dspc8682 ae66 will be generated under the same directory Steps to build ndk lib are listed below 1 Import the CCS project from C6678 1 1 2 5 packages ti transport ndk nimu directory in CCSv5 Project gt Import Existing CCS CCE Eclipse Projects 2 Clean the eth evmc6678l project and re build the project After build is completed ti transport ndk nimu ae66 will be generated under the directory C6678 1 1 2 5 packages ti transport ndk nimu lib debug 4 2 DSP DDR3 Initialization The Boot ROM codes only initialize L2 internal memory when booting from PCIE boot mode The on board DDR3 control registers need to be explicitly initialized by this supplied example program User has to initialize DDR3 control registers before loading the application into DSP After initialization of DDR3 control registers this program will clear boot address and Trusted ePlatform Services AD ANTECH Advantech Confidential wait dsp_loader to write new entry point in boot address When boot address is updated this program will jump to new entry point and start to run the next program 4 2 1 Build Instruction Steps to build DDR3 initialization program are listed below 1 Import the demo evmc66781l init CCS project from Lightning_PCIE examples ddr3 evmc6678I _ directory CCSv5 Project Import
30. boot process before BIOS scanning PCle device tree Usually DSPC 8682E can be detected after restart BIOS or reboot Linux system NOTICE The Figure 1 6 12V 6pins power connector on DSPC8682E right side must be connecting If 12V power doesn t connect the five LEDs should begin flashing to indicate the wrong power status and DSPC 8682E will not boot up Figure 1 6 The 12V 6pins power connector Trusted ePlatform Services AD ANTECH 2 Package Content Advantech Confidential This package is created to help customer quickly boot DSP through PCIE the package includes Path Purpose Lightning_PCIE dsp_loader driver DSP Program Loader Driver Lightning_PCIE dsp_loader app DSP Program Loader Utility Lightning PCIE examples ddr3 Example DDR3 Initialization Lightning_PCIE examples dsp_reset Example DSP Initialization for Local Reset Lightning_PCIE examples image_processing Example Image Processing using Multi Core Lightning PCIE examples ipc Example PC DSP Communication Lightning PCIE examples script Common demo related scripts Lightning PCIE examples web Example Simple Web Server Lightning PCIE patch Patch Platform Library and NDK Library of PDK C6678 1 1 2 5 inside MCSDK 2 1 2 5 Table 2 1 Package content list 2 1 API Interface of DSP Driver Linux based PCIE driver which is used to map between PC memory and DSP memory A prerequisi
31. build DSP loader Trusted ePlatform Services TUM Advantech Confidential 4 3 2 Usage Refer to 3 4 7 to get detailed procedure of the DSP local reset 4 4 Ethernet and Simple Web Server The Ethernet program is modified from the example codes MCSDK This example implements a simple web server running on DSP The Ethernet port on the bracket of the DSPC8682E must be connected to an external Ethernet switch support gigabit rate before running this example Each DSP has a fixed IP number that is determined by its order The pre given IP addresses are shown below The user can use a browser to view the simple web page provided by this simple web server IP DSPO 192 168 1 101 DSP 1 192 168 1 102 DSP 2 192 168 1 103 DSP 192 168 1 104 DSP 4 192 168 1 105 DSP 5 192 168 1 106 DSP 6 192 168 1 107 DSP 7 192 168 1 108 Table 4 1 DSP IP address table 4 4 1 Build Instruction Steps to build web server program are listed below 1 Import the client evmc6678l CCS project from Lightning PCIE examples web client evmc6678l directory in CCSv5 Project Import Existing CCS CCE Eclipse Projects 2 Select DSPC8682E as active configuration 3 Clean the client evmc6678l project and re build the project After build is completed client evmc6678l out client evmc6678l map will be generated under Lightning PCIEYexamples Web clientevmc6678NDSP C8682E
32. ch is located in the mcsdk 2 01 02 05 demos image_processing ipc The each DSP will be configured with a static IP instead of DHCP 2 8 Patch Platform Library and NDK Library There are some differences between the DSPC8682E and C6678 EVM hence developer should patch these files in the TI PDK before using it The modification is listed as below 1 The DSPC8682E uses DSPO EMACO DSP7 EMAC1 to connect to 54825 Ethernet PHY This patch adds the initialization of SGMII and change settings of SGMII port 0 and port 1 for BCM5482S Ethernet PHY Trusted ePlatform Services AD ANTECH Advantech Confidential 2 DSPC 8682E uses different DDR memory devices the parameters for initialization of DDR controller is not the same as C6678 EVM This patch supports the DDR memory device which is mounted on DSPC 8682E 3 The reference clocks of DDR and SGMII is not the same as C6678 EVM and this patch modifies the relevant MPY settings Trusted ePlatform Services AD ANTECH Advantech Confidential 3 DSP Program Loader After the whole system booting up all DSP chips stay in idle mode The PC is responsible to download DSP codes to every chip and awaken DSPs to execute the loaded codes The loader consists of a driver and a utility running in PC Linux environment This package contains source code of the program loader The developer must rebuild and install them to the Linux before starting using the Lightning board 3
33. ded into DSP The following example writes a jpg file into DSP 1 at DDR beginning address 0x80000000 by using DMA Lightning PCIE dsp loader app bin dsp loader loadbinary 1 0x80000000 0 1 home advantech test_image jpg Load Binary file home advantech test_image jpg to DSP1 start address 0x80000000 Size 0x00000000 Written to dsp 7496169 bytes Time measured 16225 us Load Binary OK 3 4 6 Save DSP Memory as a Binary File The command syntax is dsp_loader savebinary chip address size transfer type bin file name The command is to read a DSP memory section and save the data as a binary file The detailed description of each parameter is shown below chip the chip are the number of DSPs attached to the PC address read data address size read data size transfer type 0 for CPU memcpy 1 for DMA bin file name bin file name is the full path of binary file name which is saved Ur Gc The following example read 7496169 bytes DSP 1 at DDR beginning address 0x80000000 by using DMA and saves as test image output jpg Lightning PCIE dsp loader app bin dsp loader loadbinary 1 0x80000000 0 1 home advantech test_image jpg Load Binary file home advantech test_image jpg to DSP1 start address 0x80000000 Size 0x00000000 Written to dsp 7496169 bytes Time measured 16225 us Load Binary OK Lightning PCIE dsp loader app bin dsp loader savebinary 1 0x80000000 7496169 1
34. der app bin dsp_loader query list Card 0 Chip 0 Device 8682 Chip 1 Device 8682 Chip 2 Device 8682 Chip 3 Device 8682 Chip 4 Device 8682 Chip 5 Device 8682 Chip 6 Device 8682 Chip 7 Device 8682 Lightning_PCIE dsp_loader app dsp_loader query 7 PCI Bridge 2 PCI Bus Num 10 Vendor ID 0 104 Device ID Oxb005 Subsystem VendorID 0 13 Subsystem DevID 0 8682 Class 0x00048000 Header 0 Irq Pin 1 BAR Configuration Start Length Flags 000 00004096 0 00020200 Oxdf000000 16777216 0 00021208 0 000000 16777216 0 00021208 0 000000 33554432 0 00021208 3 4 2 Download DSP Program Image The command syntax is loader load chip core image entry point image file name hex Trusted ePlatform Services AD ANTECH A Advantech Confidential The command is to download a DSP program DSP image into to RAM of a specified DSP The detailed description of each parameter is shown below 1 chip the chip are the number of DSPs attached to the PC 2 core core is used to notify individual core range from 0 to 7 within DSP to run 3 image entry point image entry point is the start address of the loaded image User can find the entry point symbol of c 00 in the map file For example init map information is displayed in List 3 1 The reader can find the entry point of the program in the top of map file kkkk
35. dress The boot magic address is the lasted DWORD of L2 memory for C6678 the address is 0x0087FFFC pcie drv dsp write Write to DSP memory using memcpy over PCle pcie drv dsp read Read from DSP memory using over PCle pcie drv dma mem alloc Allocate contiguous host memory for specified DSP pcie drv dma mem free Free the allocated physical memory and unmap all host memory for specified DSP pcie drv dma write Write data to DSP memory from provided contiguous host memory pcie drv dma read Read data from DSP memory to provided contiguous host memory pcie drv dsp int select Wait interrupt signal from DSP pcie drv get dsp dev info Get PCle information of all DSP devices Table 2 3 User Mode Driver API List 2 2 DSP Program Loader Utility DSP program loader utility contains a hex parser and is used to load hex files into DSPs and notify DSPs to run program 2 3 Example DDR3 Initialization The DDR3 initialization example contains CCS project settings to build a boot image This program will initialize DDR by reading parameter that stored in EEPROM address 0x51 Offset 65500 bytes after software 0 6 release otherwise the Samsung 2Gb and Micron 4Gb Trusted ePlatform Services AD ANTECH Advantech Confidential DDR module initialization parameter are hard code setting DSP will wait loader utility to load the next program after DDR initializatio
36. ed IP number that is determined by its order The pre given IP addresses are shown below The user can use a browser to input the BMP image form web page provided by HTTP server IP DSPO 192 168 1 101 DSP 1 192 168 1 102 PC Setting DSP 2 192 168 1 103 IP 192 168 1 100 DSP 192 168 1 104 Subnet Mask 255 255 254 0 DSP 4 192 168 1 105 DSP5 192 168 1 106 DSP 6 192 168 1 107 DSP 7 192 168 1 108 4 6 1 Build Instruction Steps to build image processing program are listed below 1 Import the image_processing_evmc6678l_master and image processing evmc6678l slave CCS projects from Lightning PCIEYexamplesimage processingNpc evmc6678l directory CCSv5 Project gt Import Existing CCS CCE Eclipse Projects 2 Select DSPC8682E as active configuration 3 Clean the image_processing_evmc6678l_master project and re build the project After build is completed image processing evmc6678l master out will be generated under the directory Lightning_PCIE examples image_processing ipc evmc6678l master DSPC8682E 4 Clean the image processing evmc6678l slave project and re build the project After build is completed image_processing_evmc6678l_slave out will be generated under the directory Lightning PClEvexamplesimage processing Nipe evmc6678hslave Debug 4 6 2 Usage User can use the shell script Lightning PCIE examples script DSPC8682E image_processing sh
37. gisters mapped to Oxffffc90010a16000 pci 0000 07 00 0 Major 249 Minor 4 assigned pci 0000 07 00 0 Added device to the sys file system pci 0000 07 00 0 BAR Configuration pci 0000 07 00 0 Start Length Flags pci 0000 07 00 0 Oxfbbff000 00004096 0 00040200 0000 07 00 0 0xc7000000 16777216 0 00042208 1 0000 07 00 0 0 6000000 16777216 0 00042208 pci 0000 07 00 0 0 4000000 33554432 0 00042208 pci 0000 07 00 0 TI667X registers mapped to Oxffffc90010a3e000 pci 0000 08 00 0 Major 249 Minor 5 assigned pci 0000 08 00 0 Added device to the sys file system pci 0000 08 00 0 BAR Configuration pci 0000 08 00 0 Start Length Flags pci 0000 08 00 0 Oxfbcff000 00004096 0 00040200 pci 0000 08 00 0 Oxcf000000 16777216 0 00042208 0000 08 00 0 0 000000 16777216 0 00042208 pci 0000 08 00 0 0 000000 33554432 0 00042208 pci 0000 08 00 0 TI667X registers mapped to Oxffffc90010a7c000 pci 0000 09 00 0 Major 249 Minor 6 assigned pci 0000 09 00 0 Added device to the sys file system pci 0000 09 00 0 BAR Configuration pci 0000 09 00 0 Start Length Flags pci 0000 09 00 0 Oxfbdff000 00004096 0 00040200 pci 0000 09 00 0 0xd7000000 16777216 0 00042208 pci 0000 09 00 0 0 6000000 16777216 0 00042208 1 0000 09 00 0 0 94000000 33554432 0 00042208 pci 0000 09 00 0 TI667X registers mapped to Oxffffc90010a7e000 pci 0000 0a 00 0 Major 249 Minor 7 as
38. in DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 hex hex hex hex hex hex hex hex hex hex hex hex to 0 to 0 to 0 to 0 to 0 to 0 to 0 to 1 to 1 to 1 to 1 to 1 to 1 1 Trusted ePlatform Services AD ANTECH Advantech Confidential Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX i
39. kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk TMS320C6x Linker v7 3 1 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk gt gt Linked Fri Jun 15 11 12 43 2012 OUTPUT FILE NAME lt bin init out gt ENTRY POINT SYMBOL _c_int00 address 0083b900 List 3 1 entry point in the init map 4 image file name image file name is the full path of hex file name which is loaded into DSP The following example demonstrates how to load Lightning PCIE bin DSPC8682E init hex DSP image for DDR initialization into DSP 1 and use CPU 0 to run DSP image Lightning PCIE dsp loader app bin dsp loader load 1 0 0x0083b900 Lightning_PCIE bin DSPC8682E init hex Load HEX image Lightning_PCIE bin DSPC8682E init hex to 1 0 start address 0x0083b900 Load HEX OK Note Image entry point depends on DSP image The image entry point of init hex DSP image uses address 0x0083B900 as local address for each CPU Individual local CPU address can also be transferred to DSP global address with offset For example CPU 0 local address 0x00800000 is equal to DSP global address 0x1080000 CPU 1 local address 0x00800000 is equal to DSP global address 0x1180000 3 4 3 DSP Memory Read The command syntax is Trusted ePlatform Services AD ANTECH Advantech Confidential dsp_loader rmem chip address The command is to read a 32bits DWORD from DSP The detailed description
40. l console implementation and the debug message will be written into L2 memory PC host can use dsp_demo console command to dump these messages for debug purpose Trusted ePlatform Services AD ANTECH Advantech Confidential 4 5 5 IPC Demo SYS BIOS DSP Application The IPC feature also works in Tl s SYS BIOS architecture The demo program is embedded in the Ethernet example to show how to register an interrupt in SYS BIOS architecture In order to run this IPC demo users can follow two steps below 1 Initialize DDR3 module perform init 1000 sh 2 Run SYS BIOS IPC demo script perform ipc SYSBIOS sh Lightning PCIE examples script DSPC8682E ipc SYSBIOS sh 1 Translating to Intel format f web client evmc66781 DSPC8682bE client evnc66781 0out gt text c 1 100 web client evmc66781 DSPC8682bE client evmc66781 out gt web client evmc66781 DSPC8682bE client evmc66781 o0ut gt const _ web client evmc66781 DSPC8682E client_evmc66781 out gt Switch 1 web client evmc66781 DSPC8682bE client evmc66781 out gt 5 web client evmc66781 DSPC8682E client_evmc66781 out gt Switch 2 web client evmc66781 DSPC8682E client_evmc66781 out gt cinit Load HEX image bin DSPC8682E client_evmc66781 hex to 1 0 start address 0x80300000 Load HEX OK DDR of DSP is initialized ready to write dummy data to DSP dump dummy_buffer before
41. mage start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 hex hex hex hex hex hex hex hex hex hex hex hex hex to 1 to 2 to 2 to 2 to 2 to 2 to 2 to 2 to 3 to 3 to 3 to 3 to 3 Trusted ePlatform Services AD ANTECH Advantech Confidential Load HEX image start address Load HEX O
42. mage to Process les image processingiimagesievmc6678l 1920x1080 5 93MB bi Lightning PCIE sexamples image processing images evmc65781 1920x1080 5 93MB bmp Note 8 24 bit bitmap BMP images are supported BIOS MCSDK Image Processing Demonstration Version 1 00 00 03 ER mE far 4104 2 Figure 4 8 Image Processing Input Page Trusted ePlatform Services AD ANTECH Advantech Confidential Multicore Image Processing Demonstration Output Windows Internet Explorer 5 192 168 1 108 BRO iE RC TAC BARE Multicore Image Processing Demonstration Output AAD IRO a Multicore Image Processing Demonstration Output maga Processing Function mage Dimension In pixels input image Size In bytes Number of Coras Used Processing Time input image Output image sms 4 AA Figure 4 9 Image Processing Output Page
43. n finished A file format conversion tool provided by is also included and can be used to convert out file format into hex file format 2 4 Example DSP Initialization for Local Reset The DSP reset example contains CCS project settings to build a boot image This program is a part of DSP local reset procedure By running this program coreO will poll PCle legacy INTA that is generated from host Other cores will enter idle state after local reset related registers are set by DSP Program Loader 2 5 Example Simple Web Server A web demo example contains CCS project settings to build an image It can set up a web Server so user can use network browser to access the web page stored in the DSP This program is modified from TI MCSDK example which is located the mcsdk 2 01 02 O5vexamples dk client The each DSP will be configured with a static IP instead of DHCP 2 6 Example PC DSP Communication This example contains two parts a DSP image and a PC utility The dsp folder included contains CCS project settings of building an image This example provides sample codes on how to communicate between PC and DSP 2 7 Example Image Processing The image processing demo example contains two CCS project settings to build the demo images This application will run image processing kernels imagelib on multiple cores to do image processing eg edge detection etc on an input image This program is modified from TI MCSDK example whi
44. rocessing 66781 master hex to 2 0 start address 0x0c000000 Load HEX OK Load HEX image bin DSPC8682bE image processing evmc66781 master hex to 3 0 start address 0x0c000000 Load HEX OK Load HEX image bin DSPC8682bE image processing evmc66781 master hex to 4 0 start address 0x0c000000 Load HEX OK Load HEX image bin DSPC8682bE image processing 66781 master hex to 5 0 start address 0 0 000000 Load HEX OK Load HEX image bin DSPC8682bE image processing evmc66781 master hex to 6 0 start address 0x0c000000 Load HEX OK Load HEX image bin DSPC8682bE image processing 66781 master hex to 7 0 start address 0x0c000000 Load HEX OK 3 Please refer to the Figure 4 8 Input the BMP image form the internet browser The URL of DSPs are http 192 168 1 10X X 1 8 Select the number of core and image path for processing 4 The output result is shown in Figure 4 9 Trusted ePlatform Services AD ANTECH et Advantech Confidential Multicore Image Processing Demonstration Windows Internet Explorer gt i 1921681108 192 168 1 SHO BOREU t ATH 1 1 M oy BRE 168 104 O amp AED IRO 1 1 1 1 lt ocessing Demonstration Number of Cores Eight Image processing Ninction Edge Detection Select I
45. rt the CCS project from 6678 1 1 2 5 packages ti platform dspc8682 platform_lib directory in CCSv5 Project gt Import Existing CCS CCE Eclipse Projects 2 Refer to Figure 4 1 Figure 4 3 and select Lite as active configuration in CCSv5 Project Properties Trusted ePlatform Services AD ANTECH Properties for platform lib 6781 type filter text CCS Build Resource C C Build Advantech Confidential Reterenees Run Debug Settings 1 Configuration IT AN configurations Multiple i Project settings Device Variant Device Endianness Code Generation tools Output Format Debug Debug Active Debug_BE tions select filter TI v7 3 1 L Figure 4 1 Select Lite as Active Configuration Step 1 Menage Configurations 2 Figure 4 2 Select Lite as Active Configuration Step 2 Trusted ePlatform Services AD ANTECH TA Advantech Confidential Configuration Lite E General Output iD Figure 4 3 Select Lite as Active Configuration Step 2 3 Clean the platform lib dspc8682 project and re build the project After build is completed the ti platform dspc8682 lite lib will be generated under the directory C6678 1 1 2 5 packages ti platform dspc8682 platform_li
46. ry from PC 2 Read back data blocks from DSP memory to PC 3 PCinterrupts DSP 4 DSP interrupts PC 5 Emulate console output The implementation enables the DSP to display messages to PC This could be helpful when developing and debugging DSP applications 4 5 1 Build Instruction Steps to build ipc DSP program are listed below Trusted ePlatform Services AD ANTECH 1 Import Advantech Confidential the demo evmc6678l CCS project from Lightning PCIEvYexamplesNpcdspevmc6678l directory in CCSv5 Project gt Import Existing CCS CCE Eclipse Projects 2 Select DSPC8682E as active configuration 3 Clean the demo evmc6678l project and re build the project After build is completed demo_evm6678l out and evm6678l map be generated under Lightning _PCIE examples ipc dsp evmc6678l bin DSPC8682E directory 4 5 2 Usage User can use shell script file Lightning PCIE examples script DSPC8682E ipc sh to load demo evm6678l hex into the specific DSP The script will do following four jobs 1 Convert out to hex 2 Load dem evm6678l hex to the specified DSP 3 Run the PC DSP intercommunication demo repeat 1000 times 4 Runthe console output demo There two Steps to launch IPC example 1 Perform init 1000 sh to initialize DDR 2 Runipc sh The following example captures the result of running Lightning PCIE examples scrip DSPC8682E ipc sh Refer to 4 5 4 DSP Demo Program
47. s the CGI post operation to command the DSP to generate simple HTTP response pages based on current status The HTTP server also supports the CGI get operation For example these links are equivalent to the selections on the form above Display Address Information inform cgiTipinfo Display Sockets Usage inform cgi sockets Display Table inform cgi route Here is a second example CGI form This form demonstrates posting data in both the standard and multi part formats It also demonstrates the use of authentication The username and password required to access the form are username and password Authenticated CGI Form Example 4 994 Figure 4 4 TCP IP Demo Page Trusted ePlatform Services AD ANTECH Advantech Confidential http 192 168 1 108 1nform cgi Windows Internet Explorer hin 192 1681 108 avonn er pl BRO ARDO RAO BREA TAG HAU BRE http 192 1681 108 nfomcgi A A IP Address Information HTTP Server IP Address 192 168 1 108 HTTP Server Hostname No DNS Reply Your IP Address 192 168 1 1 Your Hostname No DNS Reply Return to Main Page Figure 4 5 IP Address Information page 4 5 Communication between PC and DSP This example demonstrates several functions for manipulating the DSPs including 1 Write data blocks to DSP memo
48. signed pci 0000 0a 00 0 Added device to the sys file system pci 0000 0a 00 0 BAR Configuration pci 0000 0a 00 0 Start Length Flags pci 0000 0a 00 0 Oxfbeff000 00004096 0 00040200 0000 0 00 0 Oxdf000000 16777216 0 00042208 1 0000 0 00 0 0 000000 16777216 0 00042208 0000 0 00 0 0 000000 33554432 0 00042208 pci 0000 0a 00 0 TI667X registers mapped to Oxffffc90010e92000 3 4 DSP Loader Utility DSP loader offers the functions to load the program into DSP memory and notify the DSP to run program 3 4 1 Query DSP Information The command syntax is Trusted ePlatform Services AD ANTECH Advantech Confidential dsp_loader query list or dsp_loader query dsp_loader query chip The command is to display the PCI information of DSP which are installed in the system The more detailed information will be displayed when user specify the chip parameter The chip are the number of DSPs attached to the PC Since there are eight DSP devices on the DSPC8682E this parameter can be set into 0 7 for those PC systems installed with one DSPC8682E card For those PC systems installed with two DSPC8682E cards there will be sixteen chips available to the PC systems and the parameter can be set into 0 15 The following two examples demonstrate the result of query command when PC system install DSPC8682E card and query the detailed information of DSP 7 Lightning_PCIE dsp_loa
49. silicon Version PG2 0 DSP maximum frquency limit 1GHz Load HEX image bin DSPC8682E init hex to 7 0 start address 0x00830000 Load HEX OK 4 3 DSP Local Reset After DSP code is downloaded once the DSP runs downloaded code In order to re download the different DSP code the DSP local reset function is needed When user perform the reset function by DSP loader utility the utility will configure related registers of each module of DSP and download the DSP reset program to each core The file format conversion tool is also included and can be used to convert out file format into h file which will be used as the source file when make DSP loader utility 4 3 1 Build Instruction Steps to build DSP reset program are listed below 1 Import the pcieboot_localreset CCS project from Lightning_PCIE examples dsp_reset build directory in CCSv5 Project gt Import Existing CCS CCE Eclipse Projects 2 Clean the pcieboot_localreset project and re build the project After build is completed pcieboot localreset out and pcieboot localreset map will be generated under Lightning dsp_reset build bin directory 3 Enter in Lightning_PCIE examples script utils elf2HUtils and launch pcieboot_localreset_elf2HBin sh After the steps of script are completed the pcieLocalReset h will be generated under Lightning_PCIE dsp_loader app inc 4 Enter in Lightning PCIEV make clean and make follow chap 3 2 to re
50. t 1 image processing ipc evmc66781 master DSPC8682bE image processing e vmc66781 master out gt const 2 image processing ipc evmc6678 master DSPC8682bE image processing e vmc66781 master out gt switch 1 image processing ipc evmc66781 master DSPC8682bE image processing e vmc66781 master out gt vecs image processing ipc evmc6678 master DSPC8682bE image processing e vmc66781 master out gt switch 2 Trusted ePlatform Services AD ANTECH Advantech Confidential image processing ipc evmc6678 master DSPC8682bE image processing e vmc66781 master out gt cinit Load HEX image bin DSPC8682E image processing evmc66781 slave hex start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address Load HEX OK Load HEX image start address 0x0c100000 bin DSPC8682bE image processing evmc66781 slave 0x0c100000 b
51. te for DMA to function is that memory needs to be contiguous in physical memory Memory allocated using malloc is not contiguous Ubuntu Linux doesn t have any user mode APIs to allocate contiguous physical memory and hence a Kernel mode driver to allocate contiguous physical memory is necessary Currently the implemented controls are listed below IOCTL code Description 667 IOCTL GET BAR INFO Get the current BAR information of the specified window Tl667x PCIEEP IOCTL DMA BUFFER ALLOC Allocate buffers of contiguous in physical memory for specified DSP Tl667x PCIEEP IOCTL DMA BUFFER FREE Free all allocated buffers for specified DSP Tl667X PCIEEP IOCTL GET PCI INFO Get PCI Information of DSP Trusted ePlatform Services AD ANTECH Advantech Confidential Table 2 2 Kernel Mode Driver I O Control Code List A user mode driver is also provided Developers can implement their own application based on this user mode PCle driver The APIs are listed below Export API Description pcie_drv_open Open the devices which are registered by kernel driver and set up the access of PCle BAR regions pcie_drv_close Close the devices and free all allocated resources pcie_drv_set_ep_config Set PCle endpoint related configurations such as interrupt and privilege register pcie drv dsp set entry point Write the entry point to boot magic ad
52. to setup image Trusted ePlatform Services AD ANTECH Advantech Confidential processing program on each DSP automatically The following steps set up image processing program on 8 DSPs 1 2 Perform init_1000 sh to initialize DDR Run image processing sh it will convert out file to hex and load the images to each DSP Lightning_PCIE examples script DSPC8682E image_processing sh 8 Translating to Intel format image processing ipc evmc66781 slave Debug image processing evmc66 781 slave out gt text c 1 100 image processing ipc evmc66781 slave Debug image processing evmc66 781 slave out gt text image processing ipc evmc66781 slave Debug image processing evmc66 781 slave out gt const image processing ipc evmc66781 slave Debug image processing evmc66 781 slave out gt switch image processing ipc evmc66781 slave Debug image processing evmc66 781 slave out gt vecs image processing ipc evmc66781 slave Debug image processing evmc66 781 slave out gt cinit Translating to Intel format image processing ipc evmc6678 master DSPC8682bE image processing e vmc66781 master out gt text c 1 100 image processing ipc evmc66781 master DSPC8682bE image processing e vmc66781 master out gt text image processing ipc evmc6678 master DSPC8682bE image processing e vmc66781 master out gt cons
53. vices AD ANTECH Advantech Confidential 3 3 Installation and Usage Linux host PCIE driver is used to create mapping between PC memory and DSP memory Users can run the shell script load sh to load and install the driver The script unload sh is used to unload the driver Lightning PCIE dsp loader driver module sh load sh Lightning PCIE dsp loader driver module sh unload sh The device information is shown by dmesg command Lightning PCIE dsp loader driver module dmesg dspc868x pcie ep Found TI667x PCIe EP QOxffff880073ab6000 dspc868x pcie ep Found TI667x PCIe EP QOxffff880073ab7000 dspc868x pcie ep Found TI667x PCIe EP QOxffff880073510000 dspc868x pcie ep Found TI667x PCIe EP QOxffff880073511000 dspc868x pcie ep Found TI667x PCIe EP QOxffff880073512000 dspc868x pcie ep Found TI667x PCIe EP QOxffff880073513000 dspc868x pcie ep Found TI667x PCIe EP QOxffff880073514000 dspc868x pcie ep Found TI667x PCIe EP QOxffff880073515000 dspc868x pcie ep detect 8 DSP in this system pci 0000 03 00 Major 249 Minor 0 assigned pci 0000 03 00 Added device to the sys file system pci 0000 03 00 BAR Configuration pci 0000 03 00 Start Length Flags pci 0000 03 00 Oxfb7ff000 00004096 0 00040200 0000 03 00 0 7000000 16777216 0 00042208 0000 03 00 0xa6000000 16777216 0 00042208 0000 03 00 0 4000000 33554432 0 00042208 pci 0000 03 00 pci 0000 04 00 pci 0000 04 0
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