User Manual Bus Monitor
Contents
1. S3 Temporarily CPU free run if single step execution selected see Table 4 as long as being pushed down Table 5 Push Buttons 2 4 Display The Z80 Address and Data Bus or the PIO content may be displayed via the 6 digit LED displays DIS302 DIS301 red and DIS303 green In Bus Monitor mode the red displays show the current state of the address bus while the green display shows the data bus content Adr 15 8 or Adr 7 0 or Data 7 0 or I O Adr 52h I O Adr 51h I O Adr 50h Photo 4 Display Readout on CPU Reset In PIO mode there are three eight bit wide output registers at I O addresses 50h through 52h They can be written at by CPU OUT commands any time If switch 7 of S602 S4 is off the register content is displayed see Table 4 Reading from these locations via the CPU IN commands is also possible any time DIS302 and DIS301 show the content of the I O addresses 51h and 52h 12 Blunk electronic at www train z de The output of the register at location 5Oh is of open drain characteristic and is connected to JP601 see Table 3 on page 10 The very bit of this register set to H may serve as input channel to read the status of the PIO signals at JP601 DIS303 green shows the content of that register As this is a self assembly kit the displays need to be soldered or plugged by the user 2 5 CPU control LEDs These green LEDs indicate High Low transitions or negative edges occurring on the Z80 control sig2. JP101 holds the data bus D 7 0 JP103 holds the address bus A 15 0 The control signals are distributed on both JP101 and JP103 Drawing 2 shows the their pins If ribbon cables get plugged on both of them the result is a GND signal between two bus signals Most suitable are IDE ribbon cables used in many PCs Photo 3 page 6 Table 1 on page and Table 2 on page 8 give the signals connected to JP101 and JP103 All 3 3V signals of the system bus going to the peripherals are connected to JP102 and JP104 If not noted otherwise the DC input output specifications of these pins are to be found in the XC95288XL datasheet at WWW XIilinx com Note All wires of the IDE ribbon cables must be accessible Photo 3 40 pin IDE connector Blunk electronic at www train z de 1 3 5 7 9 11 13 GND 15 17 19 21 23 25 2 29 31 33 35 37 39 Table 1 Z80 system bus signals connected to JP101 JP102 Blunk electronic at www train z de 7 B mE amp m o e m o o o 1 3 5 7 9 11 13 GND 15 17 19 21 23 25 2 29 31 33 35 37 39 Table 2 Z80 system bus signals connected to JP103 JP104 8 Blunk electronic at www train z de 2 2 PIO and Debug Connector Drawing 3 pins of JP601 The eight 3 3V PIO channels are to be found at JP601 Further on signals for debugging schmitt trigger in outputs and CPU RESET are accessible there If not noted otherwise the DC input ou
3. OER T d BLUNK ELECTRONIC PRODUCT BRIEF Self Assembly Kit Z80 Bus Monitor amp Cycle Stepper User Manual Please read carefully before power up Doc Version 2013 10 28 1 Author Mario Blunk Firmware Version V1 1 Hardware Version V1 1 Blunk electronic at www train z de Table of Contents uice e Tr ores nance ET 3 Z MAWA O IET TU mmm 4 2 1 Z60 5yStem Bus CONNECTS eei dnte comb Missus Misenum tutes ud ame ccu odas Ocio bas eiue 6 22 PIO andDebug Ee lt T Te e 9 2 9 SWITCHES ahd PUsH BHttOriSsoi e ct hee heo ee Rana aou at adn Lon tad du o dt S Rd eda PU d 11 ZR Bio MU 12 2O OPUCONVOLLEE DS m 13 2G JAGT IEEE AO cm 13 2 Schematics and Assembly DrawiGS ccccssesccceceesseceeeseeeeeeeseeeeeeeseeeeeeeessaeeeeesees 14 2 0 OW GI OUDDIV a utestabecre E E E LL a LED d 14 3 Self Assembly Shipment ODIUOFR aiat ia eoo ot ae ee qut ctv ene true tege et eet d o as 15 A RORO CONORT e OL o EE 15 SR IUNII S RETE 16 b EUS aU MC uoo asc sean ima cR MEME E EC LE rM EI Seana EE n ta c Er edo eee CLADE ETE 17 1 Preface With the objective of improving System TRAIN Z toward a development system a bus monitor in connection with a cycle stepper circuitry was an immanent user demand So a peripheral extension with these components has been designed The whole unit further on just referred to as Bus Monitor fits on a single euro sized four layer board 160 x 100 mm oee
4. Photo 1 It is fully programmable via any hardware description language like Verilog or VHDL The HDL design presented here has been written in Verilog on the Xilinx System ISE System TRAIN Z does not aim to compete with the powerful and sophisticated embedded computer systems of today Photo 1 Bus Monitor and Cycle Stepper Blunk electronic at www train z de 3 What is the Bus Monitor good for Single Step Z80 mnemonics execution Please have the list file handy Address Data and Control signal Debugging PIO mode to control user specific hardware Level Shifter from 5V Z80 world to 3 3V peripheral world Direct mounting on top of System TRAIN Z via standoffs 2 Hardware 3 3V Bus Signals PIO amp DEBUG DATA EXT qme alk LA as boh s m HSE E RD o t r we Eu MRO bid e o0 E EH o1 xis ev JES c ix x J re E BRS B Ae uo ago HN G MD uiid K XU 599049009 es ns e BSRG gom LULU a kA uau A Bia on HR 3 3V Bus Signals Y E E tz vy 390090000 JTAG Push Buttons amp Mode Switch 3 3V power in Photo 2 Bus Monitor Top View 4 Blunk electronic at www train z de CPU control LEDs BUS MONITOR Drawing 1 Bus Monitor Block Schematic Blunk electronic at www train z de 2 1 Z80 System Bus Connectors Drawing 2 pins of JP101 JP102 and JP103 JP104 All 5V signals of the system bus coming from the Z80 CPU are connected to JP101 and JP103
5. nals On edge detection the LED affected flashes for about 0 1 seconds See Photo 2 on page 4 The meaning of the LEDs is self explaining Note The status of the CPU REFRESH signal is not displayed via an LED 26 JIAG IEEE 1149 1 To program the CPLD the IEEE1149 1 signals are accessible via JP105 SeeTable 6 Pin Meaning comments 1069 of m 2G p om o 0 0 ADE a 4 Ls 3 Z Ls 1 aE Xilinx Programming Drawing 4 pins of E S3 vee 2 4 6 8 Table 6 JTAG signals NOTE Some boundary scan masters may not require a reference voltage or may even get damaged if this voltage is provided by the Bus Monitor To disconnect the reference voltage provided by the Bus Monitor from JP105 please Blunk electronic at www train z de 13 remove the jumper from JP106 2 Schematics and Assembly Drawings As these drawings are updated from time to time they are not included in this document Please find them at http www train z de train z hw 2 8 Power Supply The operating voltage of 3 3V into X101 Please refer to the assembly drawing for labeling of X101 The green LED D101 displays the presence of the operating voltage Table 7 power consumption MMU Warning The board does NOT provide any protection against overvoltage or wrong connecting of the power lines The tolerance of the 3 3V operating voltage must meet the specifications given in the Xilinx XC95288XL datasheet Bey
6. ond this limits malfunctions or damage of the board may occur 14 Blunk electronic at www train z de 3 Self Assembly Shipment Option You may order just the bare boards of the Bus Monitor without any devices soldered on it 4 RoHS conformity The Bus Monitor board without the displays is ROHS compliant Blunk electronic at www train z de 5 Useful Links Debug your hardware with the Logic Scanner at http www train z de logic_scanner Logic_ Scanner UM pdf Session Edit View Bookmarks Settings Help Logic Scanner 48 Bit Signal Memory Level amp Pulse Detectors 8 Bit Pattern Detector UUT TARGET 16 Blunk electronic at www train z de Z A complete embedded Z80 system can be found at http www train z de train z Ihe Free and Open Productivity a LibreOffice Suite LibreOffice at htto www libreoffice or The Document Foundation Z80 Verilog and VHDL Cores at http www cast inc com and http opencores org Z80 Application Notes at http www train z de train z index html EAGLE an affordable and very efficient schematics and layout tool at http www cadsoftusa com 6 Disclaimer This manual is believed to be accurate and reliable do not assume responsibility for any errors which may appear in this document reserve the right to change devices or specifications detailed herein at any time without notice and do not make an
7. tput specifications of these pins are to be found in the XC95288XL datasheet at WWW Xilinx com Blunk electronic at www train z de 9 bnm Jaga mens 2 o0 WPut pfessoragisddV S o WPuk pfessbraginsdaV e o3 WPut pfessoragistddV M pos Tee araa e 8 M so p INO Complies with specs of a CD4093 operated at 3 3V 10k Pull Up Resistor against 3 3V SI IN1 Complies with specs of a CD4093 operated at 3 3V 10k Pull Up Resistor against 3 3V DEBUG1 10k Pull Up Resistor against 3 3V DEBUG2 10k Pull Up Resistor against 3 3V DEBUG3 10k Pull Up Resistor against 3 3V DEBUG4 10k Pull Up Resistor against 3 3V 32 SI OUTO Complies with specs of a CD4093 operated at 3 3V SI OUT Complies with specs of a CD4093 operated at 3 3V 9 11 13 15 17 19 GND 21 23 25 27 29 31 33 35 37 39 y nocomnection Table 3 PIO and Debug Signals at JP601 10 Blunk electronic at www train z de 2 3 Switches and Push Buttons The operating mode of the Bus Monitor is to be set via the 8 fold DIL Switch S602 S4 Table 4 gives the operating modes available a2 o Parallel to Push Button S603 S2 7 on display shows bus address and data in CPU free run or single step mode 8 o Parallel to signal RSV GCK2 Table 4 DIL Switch S602 S4 Blunk electronic at www train z de 11 Push Button Mode Meaning S601 S1 Reset CPU S603 S2 CPU next cycle if single step execution selected see Table 4 S604
8. y commitment to update the information contained herein do not assume responsibility for any design errors which may appear in the hardware nor in the software of this product nor for modifications made by the user This product is not authorized for use as critical component in life support devices or systems opecifications mentioned in this manual are subject to change without notice My Boss is a Jewish Carpenter Blunk electronic Oolder Mario Blunk Buchfinkenweg 5 99097 Erfurt Germany 449 0 176 2904 5855 http www train z de 2013 Mario Blunk Printed in Germany Blunk electronic at www train z de 17
Download Pdf Manuals
Related Search