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Hynix 16GB DDR3 PC3-12800

1. m o 02 T i F TE J 4 i 9 5a HHH E g lt 5 1 L Mi bas Ze Ed 3 E Z DO 3 0 D27 DQ 3 0 D26 g o 2 82 vis 5 w ke w 8 5 E re e 0 bas Das DOS 5 DQS S ZW re D25 poo D24 S w Be 2 wesw 5 E La 0 bas Sie S g Sr g W DQ 3 0 D23 DQ 3 0 D22 S w 218 5 we w 5 E Weg e e 0 bas Sie MEn BM g W DQ 3 0 D21 DQ 3 0 D20 8 w 2188 588 we w 5 E all e e bos as ia g ERE g W pq 3 0 D19 DQ 3 0 Pis w 21848 5 882 wesw 5 e gt e lt lt o TIT TTE ATH TEES db SI 5505 mo 5 gt J j j J uj u P qp I I zQ ZQ DOS DOS S j E DQ 3 0 D63 Beech D62 015519 w 3 w lils w 8 E Ly t e zQ ZQ Die Dos S x S DQ 3 0 D65 DQ 3 0
2. 1 DQ to 1 O wiring may be changed within a nibble 2 Unless otherwise noted resistor values are 15 Ohms 5 3 See the wiring diagrams for all resistors associated with the command address and control bus might be changed on customer s requests For more details of SPD and Thermal sensor please contact local Hynix sales representative 4 ZQ resistors are 240 Ohms 1 For all other resistor values refer to the appropriate wiring diagram Rev 1 0 Aug 2012 22 2 8 55555 ee g METETE 8 2 x TETTERE E i8 3 EL i d ESS il 94404441 i db l L l l M RA YA os VS w Sds VSS pa SCH M DQS s DQS s DQS g DQS g E 3 0 D29 EAEOI D28 See D61 Bere D60 v 92 wie w 8 5 wiki g w 8 amp w 88 8 5 La Las L m RA VSS yal RA VSS AA RA VSS A En w DOS 5 DQS s DOS S8 DQS s z DM z DM Z z DO 3 0 D31 DQ 3 0 D30 DQ 3 0 D59 EG D58 w klag s
3. m n im n on S nana aU JO 5 GE a gig 5 TTE 3 Si 1 1 L L L ji DQ513 w DOS DOS DQS13 W DQS n DQs VSS DM 2 DM E DQ 39 36 DQ 3 0 D13 DQ 3 0 D31 S88 swe 5 wBie sw 8 s Des Alpe m hos DQS5 W DOS 2 DOS vsS DM 9 DM 9 DQ43 40 MW DQ 3 0 D5 DQ 3 0 D23 E 8 S 28 5 iles 8 DQS15 A DOS p pos DQS15 W DOS DOS vsS DM DM B DQ 55 52 MM DQ 3 0 D15 DQ 3 0 D33 8 9 i 28 s 8 8 5 a 218 5 DQS6 A DOS pos DQS6 w DOS DOS VSS DM e DM 9 DQ 51 48 MM DQ 3 0 D6 DQ 3 0 D24 8 2 RIR S RIR 5 i BB RRR 92 Vtt VW VDDSPD VDDSPD SA0 SA0 EVENT EVENT SPD with SAL SA1 SCL SCL E SA2 SA2 SDA SDA VSS VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer s requests For more details of SPD and Thermal sensor please contact local SK hynix sales representative 18 SK yi 16GB 2Gx72 Module 2Rank of x4 page3 S0 mw RS0A C50 SDRAMs D 3 0 D 12 8 D17 sa 1 2 RS0B CS0 SDRAMs D 7 4 D 16 13 S1 g BSA gt CST SDRAMs D 21 18 D 3026 D35 RS1B gt CST SDRAMs D 25 22 D 34 31 BA N 0
4. vss vss w vss w m m oF D cs HUL Die z Z ER ed LI 1 I II DQS4 N DOS ZO DQS13 N DOS 2 past w DOS DQS13 N DOS i n vss DM e DQ 35 328 W DQ 3 0 D4 H Misa amd DQ 3 0 D13 z 2 wie 8 5 io BB RIRE Ble I poss w pos 70 A posi w pos zs DQS5 d DOS _ DOS w D5Qs cc vss DM g vss DM E DQ 43 4044M DQ 3 0 D5 Z DQIA47 444 A DQ 3 0 D14 z 2 wes 8 5 w Be RIRE Ble I KL La e e e pose DS 70 posis w os 2 R A DOS z DQS15 DQS z DM ra vss DM e DQ 51 488 A DQ 3 0 D6 E Miss aad Do 13 01 D15 S z 2 u 28 BE i BBE BIg I e e L e DQS7 dd DOS zQ DQS16 w oos za D I apos z H 09516 w pos S DM E vss DM DQ 59 56F We DQ 3 0 D7 E H Mies emil DA 13 01 D16 2 2 y wle 5 w BB RIRE Ble I e e La e e Vtt 3 See the wiring diagrams for all resistors associated with the com mand address and control bus 4 ZQ resistors are 24096 Rdr all other resistor values refer to the appro priate wiring diagram
5. EM LJ Cc C D Cc mu 15 36 22 00 Side 7 19mm max HH q M 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated 2 In order to uninstall FDHS please contact sales administrator Units millimeters Rev 1 0 Aug 2012 68 SK nix 4Gx72 HMT84GR7MMR4C Front lt 133 35 gt i 128 95 Detail B gt 2 10 0 15 Wl a sms z Detail A 05 C x DDP DDP DDP DDP DDP DDP DDP DDP DDP I 4X3 00 0 10 ES g M g 5 AIRS B DDP DDP DDP DDP DDP DDP DDP DDP DDP AP N A r4 2X3 00 0 10 CO v E 47 00 gt lt l Detail C 5 0 Detail D Back _SPD H J DDP DDP DDP DDP i DDP DDP DDP DDP DDP L 2g 5 SS DDP DDP DDP DDP DDP DDP DDP DDP DDP C Om HHIHH 2x R0 75 Max Side Detail of Contacts A Detail of Contacts B Detail of Contacts C Detail of Contacts D 343mm max 1 20 0 15 om dus ER d 14 90 gt lt 250 13 60 gt _ 3 E 8 E d 3 0 1 SS E i 2 d Y N
6. a x kel m 8 28 2 E9odsgsknmi is z8 i1 ii EwWRBRE RS 2 2 8 315 om a z e R 0 0 REF 0 0 0 0 0 0 0 1 12 DD 1 0 0 0 0 00 0 3 4 DD 1 1 1 0 0 00 0 5 8 repeat cycles 1 4 but BA 2 0 2 1 2 5 9 12 repeat cycles 1 4 but BA 2 0 2 D 13 16 repeat cycles 1 4 but BA 2 0 3 E 17 20 repeat cycles 1 4 but BA 2 0 4 21 24 repeat cycles 1 4 but BA 2 0 5 25 28 repeat cycles 1 4 but BA 2 0 6 29 32 repeat cycles 1 4 but BA 2 0 7 2 33 nRFC 1 repeat Sub Loop 1 until nRFC 1 Truncate if necessary a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL 59 Rev 1 0 Aug 2012 SK ni Table 10 IDD7 Measurement Loop Pattern ATTENTION Sub Loops 10 19 have inverse A 6 3 Pattern and Data Pattern than Sub Loops 0 9 Q o R 8 og S u e d Sg EK mn e 5 28 2 SE Elel3l8lE 8S 8 8588 18 ren 0 J0 ACT 0 0 1 1 0 0 00 0 0 0 0 1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 2 D 1 0 0 0 0 0 00 0 0 0 Sas repeat above D Command until nRRD 1 nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 1 nRRD 1 RDA 0 1 0 1 0 1
7. U Uv 240 N 121 S M 2x R0 75 Max Side 3 43mm max Detail of Contacts A Detail of Contacts B Detail of Contacts C 1 204 0 15 moons 2 50 lt t 3 n S 8 8 3 0 1 8 3 K E S P S Y R y 1 00 lt is E lt o KR 1 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Aug 2012 65 SK nix 1Gx72 HMT41GR7MFR8C Front P 133 35 128 95 lt gt p 2 10 0 15 SIDE A Detail A OD a E k c mds SS t E 9 8 dco ml i e Detail B Detail C v Back U Uv 240 N 121 S M 2x R0 75 Max Side 3 43mm max Detail of Contacts A Detail of Contacts B Detail of Contacts C 1 204 0 15 moons 2 50 lt t 3 n S 8 8 3 0 1 8 3 K E S P S Y R y 1 00 lt is E lt o KR 1 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Aug 2012 66 SK ni
8. Speed Bin DDR3 800E Unit Notes CL nRCD nRP 6 6 6 Parameter Symbol min max Internal read command to first data tna 15 20 ns ACT to internal read or write delay time acp 15 ns PRE command period trp 15 ns ACT to ACT or REF command period fac 52 5 ns ACT to PRE command period ikas 37 5 9 tREFI ns CL 6 CWL 5 ck AvG 2 5 3 3 ns 133 Supported CL Settings 6 nck Supported CWL Settings 5 nck Rev 1 0 Aug 2012 43 SK nix DDR3 1066 Speed Bins For specific Notes See Speed Bin Table Notes on page 47 Speed Bin DDR3 1066F CL nRCD nRP 7 7 7 EE Poe Parameter Symbol min max nternal read command to first data TAA 13 125 20 ns ACT to internal read or write delay time bc odes i is PRE command period lap 13 125 ns ACT to ACT or REF fac 50 625 E ris command period ACT to PRE command Rs 37 5 9 tREFI e period ap CWL 5 LK AVG 2 5 3 3 ns 1 2 3 6 7 CWL 6 IcK AVG Reserved ns 1 2 3 4 oe CWL 5 IcK AVG Reserved ns 4 7 CWL 6 fk AvG 1 875 2 5 ns 1 2 3 4 mw CWL 5 IcK AVG Reserved ns 4 7 CWL 6 ewe 1 875 lt 2 5 ns 1 2 3 Supported CL Settings 6 7 8 ACK Supported CWL Settings 5 6 Nck Rev 1 0 Aug 2012 44 SK ni DDR3 1333 Speed Bins For specific Notes See Speed Bin Table Notes on page 47
9. Speed Bin DDR3 1333H CL nRCD nRP 9 9 9 ane Ite Parameter Symbol min max Internal read bA 13 5 20 command to first data 13 125 ACT to internal read or acp 13 5 ag write delay time 13 125 gt 9 PRE command period lp SE ns ACT to ACT or REF K 49 5 _ S command period 49 125 gt 9 AST ig Ge RAS 36 9 tREFI ns CWL 5 IcK AVG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 amp xiave Reserved ns 1 2 3 4 7 CWL 7 IcK AVG Reserved ns 4 CWL 5 aver Reserved ns 4 1 875 lt 2 5 CL CWL 6 IcK AVG ns 1 2 3 4 7 Optional CWL 7 f K AVG Reserved ns 1 2 3 4 CWL 5 awe Reserved ns 4 CL 8 CWL 6 ICK AVG 1 875 2 5 ns 1 2 3 7 CWL 7 lck AVG Reserved ns 1 2 3 4 CWL 5 6 fcK AVG Reserved ns 4 CWL 7 IcK AVG 1 5 lt 1 875 ns 1 2 3 4 CWL 5 6 amp kave Reserved ns 4 CL 10 1 CWL 7 fave Optional c E Supported CL Settings 6 7 8 9 10 cK Supported CWL Settings 5 6 7 NCK Rev 1 0 Aug 2012 45 SK ni DDR3 1600 Speed Bins For specific Notes See Speed Bin Table Notes on page 47 Speed Bin DDR3 1600K CL nRCD nRP 11 11 11 uar Note Parameter Symbol min max 13 75 NE Een aA 13 125 Gi a ACT to internal read or tco 13 75 i write delay time 13 125 gt 9 13 75 PRE command period lap 13 125 59 ns ACT to ACT or REF hc 48 75 i c
10. Rev 1 0 Aug 2012 SK ni Symbol Type Polarity Function Positive dat aa DQS 17 0 1 0 Edge Positive line of the differential data strobe for input and output data OP anil Negative poc e DQS 17 0 1 0 Edge Negative line of the differential data strobe for input and output data TDQS TDQS is applicable for X8 DRAMs only When enabled via Mode Register A11 1 in TDQS 17 9 MR1 DRAM will enable the same termination resistance function on TDQS TDQS that is TDQS 17 9 OUT applied to DQS DQS When disabled via mode register A1120 in MR1 DM TDQS will provide the data mask function and TDQS is not used X4 DRAMs must disable the TDQS function via mode register A11 0 in MR1 SA 2 0 IN These signals are tied at the system planar to either Vss or Vppspp to configure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into or out of the SPD EEPROM A resistor SDA 1 0 must be connected from the SDA bus line to Vppspp on the system planar to act as a pullup SCL IN This signal is used to clock data into and out of the SPD EEPROM A resistor may be con B nected from the SCL bus time to Vppspp on the system planar to act as a pullup OUT This signal indicates that a thermal event has been detected in the thermal sensing EVENT Active L device The system should guarantee the electrical level requirement is met for the Uem CuVe LOW EVENT
11. 15 mV 4 For reference approx VDD 2 15 mV 5 VIH dc is used as a simplified symbol for VI H CA DC100 6 VIL dc is used as a simplified symbol for VIL CA DC100 7 VIH ac is used as simplified symbol for VIH CA AC175 VIH CA AC150 VIH CA AC135 and VIH CA AC125 VIH CA AC175 value is used when Vref 0 175V is referenced VIH CA AC150 value is used when Vref 0 150V is referenced VIH CA AC135 value is used when Vref 0 135V is referenced and VIH CA AC125 value is used when Vref 0 125V is referenced 8 VIL ac is used as simplified symbol for VIL CA AC175 VIL CA AC150 VIL CA AC135 and VIL CA AC125 VIL CA AC175 value is used when Vref 0 175V is referenced VIL CA AC150 value is used when Vref 0 150V is referenced VI L CA AC135 value is used when Vref 0 135V is referenced and VIL CA AC125 value is used when Vref 0 125V is referenced Rev 1 0 Aug 2012 27 SK yi AC and DC I nput Levels for Single Ended Signals DDR3 SDRAM will support two Vih Vil AC levels for DDR3 800 and DDR3 1066 as specified in the table below DDR3 SDRAM will also support corresponding tDS values Table 43 and Table 51 in DDR3 Device Operation as well as derating tables in Table 46 of DDR3 Device Operation depending on Vih Vil AC lev els Single Ended AC and DC I nput Levels for DQ and DM DDR3 800 1066 DDR3 1333 1600 Symbol Parameter Unit Notes
12. A E L RBA N O A BAIN 0 SDRAMs D 3 0 D 12 8 D 21 17 D 30 20 D35 G Lu BAINO SDRAMs DL DI16 19 25 22 bt 34 31 A N 0 RA N Q A gt A N 0 SE 21 17 Diode D35 RUE A N 0 B A N 0 SDRAMs D 7 4 D 16 1 DOS DES RS s F MN RAS SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 E T RRASB gt RAS SDRAMs D 7 4 D 16 13 D 25 22 D 34 31 CAS RCASA gt CAS SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 x E RCASB CAS SDRAMs DI AL D 16 13 D 25 22 D 34 31 WE NN R RWEA WE SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 I RWEB WE SDRAMs D 7 4 D 16 13 D 25 22 D 34 31 CKE0 i RCKE0A gt CKE0 SDRAMs D 3 0 D 12 8 D17 P RCKE0B CKE0 SDRAMs D 7 4 D 16 13 DR I L F RCKEIA gt CKEI SDRAMs D 21 18 D 30 26 D35 L RCKE1B CKE1 SDRAMs D 25 22 D 34 31 ODTO I RODTOA gt ODTO SDRAMs D 3 0 D 12 8 D17 RODTOB ODTO SDRAMs D 7 4 D 16 13 ODTl J RODTIA ODTI SDRAMs D 21 18 D 30 26 D35 RODT1A gt ODTI SDRAMs D 25 22 D 34 31 CK0 PCK0A CK SDRAMs D 3 0 D 12 8 D17 PCK0B CK SDRAMs D 7 4 D 16 13 PCK1A gt CK SDRAMs D 21 18 D 30 26 D35 uc PCK1B CK SDRAMs D 25 22 Ds 31 CK0 PCK0A CK SDRAMs D 3 0 D 12 8 D17 PCKOB gt CK SDRAMs D 7 4 D 16 13 F PCK1A gt CK SDRAMs D 21 18 D 30 26 D35 CK1 Sg PCK1B CK SDRAMs D 25 22 D 34 31 CK1 2 PAR IN Err Out
13. Detailed IDD and IDDQ Measurement Loop Patterns are described in Table 3 through Table 10 IDD Measurements are done after properly initializing the DDR3 SDRAM This includes but is not lim ited to setting RON RZQ 7 34 Ohm in MR1 Qoff 0g Output Buffer enabled in MR1 RTT Nom RZQ 6 40 Ohm in MR1 RTT Wr RZQ 2 120 Ohm in MR2 TDQS Feature disabled in MR1 Attention The IDD and IDDQ Measurement Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started Define D CS RAS CAS WE HIGH LOW LOW LOW Define D CS RAS CAS WE HIGH HIGH HIGH HIGH Rev 1 0 Aug 2012 49 Y Jop Y DDQ optional C i DDR3 SDRAM CKE pos Das Att 25 Ohm CS RENS DQ DM 9 Vppo 2 RAS CAS WE TDQS TDQS A BA ODT ZQ Vss Figure 1 Measurement Setup and Test Load for IDD and IDDQ optional Measurements Note DIMM level Output test load condition may be different from above Application specific IDDQ memory channel Test Load Ul Channel IDDQ IDDQ lO Power Simulation Simulation Simulation a gt Correction Channel IO Power Number Figure 2 Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev 1 0 Aug 2012 50 De SK hynix
14. zi 0 0 1 Wi 1 00 50 0 P 5 00 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Aug 2012 69 SK ni 4Gx72 HMT84GR7MMR4C Heat Spreader Front 4 133 75 gt ne 41 9 N 3 59 lt gt I 20 9 PET 8 4 um 6 35 1 lt PREEN 5 39 8 04 CH PF a A 6 3 2 155 9 33 o Si Clg 88 4 ag 120 x N 1 rrr rr N a n r nrar e 7 36 33 4 33 4 lt gt lt p lt 46 46 3 P 80 54 x P 119 64 S 57 2 d Back ee S E T 4 s 2 7 t o B C el a A W n 121 240 Snina Side 7 19mm max isla B N 27 010mm max gt Note 1 0 13 tolerance on all dimensions unless otherwise stated 2 In order to uninstall FDHS please contact sales administrator Units millimeters Rev 1 0 Aug 2012 70
15. 2Gx72 HMT42GR7MFR4C lt I gt Detail B lt gt S e A 2 10 0 15 Ne d E Detail A C 4X3 00 0 10 L x g SZ SIE LES omia l ks X e N 28 Ao N i j He 2X3 00 0 101 d v le gt 0 Detail D LJ UJ UV 240 Ym mmm 2x R0 75 Max f Side Detail of Contacts A Detail of Contacts B ail of Contacts C Detail of Contacts D MEE 1 204 0 15 80 0 05 58 t 5 14 90 4 0 4 13 60 3 8 3 0 1 8 3 E d i 3 e n Y I N en 1 00 a 50 0 lt 500 P 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 0 Aug 2012 Units millimeters 67 SK ni 2Gx72 HMT42GR7MFR4C Heat Spreader 22 00 30 20 46 46 lt gt Le 80 54 gt Le 119 64 gt Back k 57 2 gt 2 7
16. IDD and I DDQ Specification Parameters and Test Conditions IDD and I DDQ Measurement Conditions In this chapter IDD and IDDQ measurement conditions such as test load and patterns are defined Figure 1 shows the setup and test load for IDD and IDDQ measurements IDD currents such as IDDO IDD1 IDD2N IDD2NT IDD2PO DD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET and IDD7 are measured as time averaged currents with all VDD balls of the DDR3 SDRAM under test tied together Any IDDQ current is not included in IDD currents DDQ currents such as IDDQ2NT and IDDQ4R are measured as time averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together Any IDD current is not included in IDDQ cur rents Attention IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2 In DRAM module application IDDQ cannot be measured separately since VDD and VDDQ are using one merged power layer in Module PCB Fo A IDD and IDDQ measurements the following definitions apply 0 and LOW is defined as VIN lt Vii AC max LU and HIGH is defined as VIN gt Vinac may MID LEVEL is defined as inputs are VREF VDD 2 Timing used for IDD and IDDQ Measurement Loop Patterns are provided in Table 1 Basic IDD and IDDQ Measurement Conditions are described in Table 2
17. IDD6ET 624 624 624 mA IDD7 3464 3734 3824 mA Rev 1 0 Aug 2012 61 SK ni 8GB 1GM x 72 R DI MM HMT41GR7MFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDD0 1394 1484 1529 mA IDD1 1484 1574 1619 mA IDD2N 1214 1304 1304 mA IDD2NT 1304 1394 1394 mA IDD2P0 588 588 588 mA IDD2P1 624 624 624 mA IDD2Q 1214 1304 1304 mA IDD3N 1394 1394 1394 mA IDD3P 678 678 678 mA IDD4R 1844 2024 2204 mA IDD4W 1889 2069 2249 mA IDD5B 2249 2339 2384 mA IDD6 588 588 588 mA IDD6ET 624 624 624 mA IDD7 2429 2609 2699 mA 16GB 2G x 72 R DIMM HMT42GR7MFR4C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDD0 2024 2204 2294 mA IDD1 2204 2384 2474 mA IDD2N 1664 1844 1844 mA IDD2NT 1844 2024 2024 mA IDD2P0 948 948 948 mA IDD2P1 1020 1020 1020 mA IDD2Q 1664 1844 1844 mA IDD3N 2024 2024 2024 mA IDD3P 1128 1128 1128 mA IDD4R 2744 3104 3464 mA IDD4W 2744 3104 3374 mA IDD5B 3734 3914 4004 mA IDD6 948 948 948 mA IDD6ET 1020 1020 1020 mA IDD7 3914 4274 4454 mA Rev 1 0 Aug 2012 62 SK ni 32GB 4G x 72 R DIMM HMT84GR7MMR4C Symbol DDR3 1066 DDR3 1333 Unit note IDD0 2924 3284 mA IDD1 3104 3464 mA IDD2N 2564 2924 mA IDD2NT 2924 3284 mA IDD2P0 1668 1668 mA IDD2P1 1812 1812 mA IDD2Q 2564 2924 mA IDD3N 328
18. W lt DQ 7 0 ES DQ 47 40 W DQ 7 0 a z E o FHODEPDEIEEE 0259 E LIIILILLLLI Lp p EES DQS2 w DOS ZQ DQS6 V DOS ZQ DQS2 N DOS es DQS6 NN DOS s DM2 DQS11 TDQS o DM6 DQS15 A TDQS Q SR DQSll W TDOS D2 DQSIS Jrpqs D6 DQ 23 16 W lt DQ 7 0 g DQ 55 48 W DQ 7 0 a 2 E u 6 u ko 2 28 s 5 ole 5 LT T T TT Tf ERE EE ERE ERR ET EE REIS DQS1 W Das zQ DQS7 wr DUS 20 DQS1 WNMDQS A DQS7 m DOS ES DM1 DQS10 WY TDQS 9 DM7 DQS16 W TDQS 9 Vppsrp SPD DQS 10 W TDQS D1 g DQSI6 TOS D7 T Vo p tp po p8 E 4 B DQ 15 8 DQ 7 0 E DQ 63 56 W DQ 7 0 a kg L 2 Vrr E z WEZ 168 BE 0 259 8 SEB Z VREFCA 00 08 L T T IT T LT T LI L 1 1 L T L 1 VREFDQ D0 D8 paso d Dos ZQ Na Vss D0 D8 DQSO NA DOS DM0 DQS9 W TDQS 9 L DOSS m TDOS DO DQ 7 0 n DQ 7 0 a Note o 1 DQ to I O wiring may be changed within byte DICH S E G 6 o lt 2 ZQ resistors are 240 Q 1 For all other resistor values refer to the IT rT T TL 1 appropriate wiring diagram Vtt Ww S0 L RSOA CS0 SDRAMs D 3 0 D8 SI i RSOB gt CS0 SDRAMs D 7 4 BA N 0 WY RBA N 0 A BA N 0 SDRAMs D 3 0 D8 2 RBA N 0 A BA N 0 SDRAMs D 7 4 A N0 R F S A N 0 SDRAMs D 3 0 D8 m E RA N 0 A A Nook SDRAMs pp RAS WM RRASA gt RAS O G RRASA RAS SDR
19. Rev 1 0 Aug 2012 Plan to use SPD with Integrated TS of Class B and might be changed on customer s requests For more details of SPD and Thermal sensor please contact local SK hynix sales representative Vppsep 34 SPD VDD D0 D17 Ver D0 D17 VREFCA A D0 D17 VREFDQ D0 D17 Vss D0 D17 13 SK yi 8GB 1Gx72 Module 1Rank of x4 page2 S0 mw m SE ege BA N 0 R F AN EL SS G RAS L WE N E F CKE0 w DTD CK0 CKO PAR IN GERR RESET RST RSOA gt CS0 SDRAMs D 3 0 D 12 8 D17 RSOB CS0 SDRAMs D 7 4 D 16 13 RSIA CSI SDRAMs D 12 9 D17 RS1B CSI SDRAMs D 16 13 Ed gt BA N 0 SDRAMs D 3 0 RBA N 0 B BA N 0 SDRAMs D 7 4 BANS A gt A E SDRAMs DEN I D RA N 0 B A N 0 SDRAMs D 7 4 D RRASA RAS SDRAMs D 3 0 D 12 RRASB RAS SDRAMs D 7 4 D 16 8 1 RCASA gt CAS SDRAMs D 0 D I2 8 D17 T i i RWEA WE SDRAMs Dan DI12 8 pu RWEB gt WE SDRAMs DU AL D 16 1 RCKEOA CKE0 SDRAMs D 3 0 D RCKE0B gt CKE0 SDRAMs D 7 4 DI RODT0A ODTO SDRAMs D 3 0 D 12 8 RODTOB ODTO SDRAMs D 7 4 D 16 1 PCKOA CK SDRAMs D 3 PCKOB CK SDRAMs D 7 0 DS 4 PCKOA CK SDRAMs D 3 0 D8 PCKOB CK SDRAMs D 7 4 Err_Out RST SDRAMs D 17 0 S 3 2 CKE1 ODT1 CK
20. Single Ended Output Slew Rate Definition Single Ended Output slew Rate Definition Output Slew Rate single ended DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 S Units Parameter Symbol Min Max Min Max Min Max Min Max Single ended Output Slew Rate SRQse 2 5 5 2 5 5 2 5 5 2 5 5 V ns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Note 1 In two cases a maximum slew rate of 6V ns applies for a single DQ signal within a byte lane Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane are static i e they stay at either high or low Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane switching into the opposite direction i e from low to high of high to low respectively For the remaining DQ signal switching in to the opposite direction the regular maximum limite of 5 V ns applies Rev 1 0 Aug 2012 37 SK ni Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between VOLdiff AC and V
21. Table 1 Timings used for IDD and I DDQ Measurement Loop Patterns DDR3 1066 DDR3 1333 DDR3 1600 Symbol Unit 7 7 7 9 9 9 11 11 11 tex 1 875 1 5 1 25 ns CL 7 9 11 nCK Den 7 9 11 nCK Mec 27 33 39 nCK RAS 20 24 28 nCK lap 7 9 11 nCK 1KB page size 20 20 24 nCK FAW KB page size 27 30 32 nCK 1KB page size 4 4 5 nCK a 2KB page size 6 5 6 nCK Dote 512Mb 48 60 72 nCK Ngrc 1 Gb 59 74 88 nCK Ngc 2 Gb 86 107 128 nCK Ngec 4 Gb 139 174 208 nCK Ngre 8 Gb 187 234 280 nCK Table 2 Basic I DD and I DDQ Measurement Conditions Symbol Description Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL see Table 1 BL 89 AL 0 CS High between ACT and ppo PRE Command Address Bank Address Inputs partially toggling according to Table 3 Data 10 MID LEVEL DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table 3 Output Buf fer and RTT Enabled in Mode Registersb ODT Signal stable at 0 Pattern Details see Table 3 Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS nRCD CL see Table 1 BL 88 AL 0 CS High between ACT Jop RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 4 DM stable at 0 Bank Activity Cycling with on bank active at a time 0 0 1 1 2 2 see Table 4 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Ta
22. 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Table 8 IDD4W Measurement Loop Pattern Q L kel m x o lt EI By i 8 Pw ee eS ig s 8 om m SI z lt lt lt lt 0 0 WR O 1 0 0 1 0 00 0 0 0 0 00000000 1 D 1 0 0 0 1 0 00 0 0 0 0 2 3 DD 1 1 1 1 1 0 0 0 oloo 4 WR O 1 0 0 1 0 00 0 0 F 0 00110011 F 5 D 1 0 0 0 1 0 00 0 0 F 0 S 2 6 7 DD 1 1 1 1 1 0 100 0 0 F 0 E 9 1 8 15 repeat Sub Loop 0 but BA 2 0 1 8 8 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to WR Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Write Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Aug 2012 58 Ds SK hynix Table 9 IDD5B Measurement Loop Pattern
23. 53 Err_Out NC 173 VDD 114 DQ58 234 DQ63 54 VoD 174 A12 BC 115 DQ59 235 Vss 55 All 175 A9 116 Vss 236 VDDSPD 56 A7 176 VoD 117 SAO 237 SA1 57 VoD 177 A8 118 SCL 238 SDA 58 A5 178 A6 119 SA2 239 Vss 59 A4 179 VDD 120 VTT 240 VTT 60 VDD 180 A3 NC No Connect RFU Reserved Future Use Rev 1 0 Aug 2012 De SK hynix Registering Clock Driver Specifications Capacitance Values Symbol Parameter Conditions Min Typ Max Unit Input capacitance Data inputs 1 5 2 5 pF a Input capacitance CK CK FBIN FBIN 15 25 F up to DDR3 1600 i p Ge Ee RESET MIRROR Vi Vpp or GND Vp 1 5v _ 3 oF Input amp Output Timing Requirements 1066 1333 DDR3 1600 Symbol Parameter Conditions Unit Min Max Min Max fia Input clock fre Application fre 300 670 300 810 Mhz quency quency Input clock fre frEST EE Test frequency 70 300 70 300 Mhz Input valid before tsy Setup time CK CK 100 50 ps Input to remain N Hold time l Valid after CK CK im 125 ps Propagation tppu delay single bit CK CK to output 0 65 1 0 0 65 1 0 ns switching Output disable tps time 1 2 Clock ee 0 5 tQSK1 min 0 5 tQSK1 min ps prelaunch Output enable T Output driving to 0 5 g _ ten time 1 2 Clock Yn Yn tOSK1 max 0 5 tQSK1 max ps prelaunch 10 Rev 1 0 Aug 2012 SK ni On DIMM Thermal Sensor The DDR3 SDRAM D
24. DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Ipp2q Precharge Quiet Standby Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registersb ODT Signal stable at 0 Ipp3N Active Standby Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Ipp3P Active Power Down Current CKE Low External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data lO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Rev 1 0 Aug 2012 52 SK ni Symbol Description Operating Burst Read Current CKE High External clock On CK CL see Table 1 BL 89 AL 0 CS High between RD Command Address Bank Address Inputs partially toggling according to Ta
25. Ds SK hynix Pin Descriptions e Num ee Num Pin Name Description ber Pin Name Description ber CKO Clock Input positive line 1 ODT 1 0 On Die Termination Inputs 2 CK0 Clock Input negative line 1 DQ 63 0 Data Input Output 64 CK1 Clock Input positive line 1 CB 7 0 Data check bits Input Output 8 CK1 Clock Input negative line 1 DQS 8 0 Data strobes 9 CKE 1 0 Clock Enables 2 DQS 8 0 Data strobes negative line 9 DM 8 0 C Data Masks Data strobes RAS Row Address Strobe 1 DQS 17 9 Ternet 3 ee 9 TDQS 17 9 ermination data strobes ARG DQS 17 9 Data strobes negative line CAS Column Address Strobe 1 9 TDQS 17 9 Termination data strobes Reserved for optional hardware WE Write Enable 1 EVENT 1 temperature sensing I Memory bus test tool Not Con SIS Cp Selects i TEST nected and Not Usable on DIMMs 1 A 9 0 A11 a s A 15 13 Address Inputs 14 RESET Register and SDRAM control pin 1 A10 AP Address Input Autoprecharge 1 Vpp Power Supply 22 A12 BC Address Input Burst chop 1 Vss Ground 59 BA 2 0 SDRAM Bank Addresses 3 VREFDQ Reference Voltage for DQ 1 Serial Presence Detect SPD V SCL Clock Input 1 REFCA Reference Voltage for CA 1 SDA SPD Data Input Output 1 VT Termination Voltage 4 SA 2 0 SPD Address Inputs 3 Vppspp SPD Power 1 Parity bit for the Address and Par_In 1 7 Control bus Parity error found on t
26. H psp p DQS14 DOS DQS14 W DQS VSS DM o DQ 47 44 A DQ 3 0 D14 a2 u io B83 m mn n gg Y E PE l L L L L Dos DOS S D32 919199 we 8 8 A N O BA N O L DQS4 A DOS Das DQ54 w DOS DQS E VSS DM DM DQ 35 32 DQ 3 0 D4 DQ 3 0 D22 willie 5 wie 8 8 L T E DQS16 W DQS F 9 DQS16 A DOS e DOS E vSS DM DM 9 DQ 63 60 A DQ 3 0 D16 DQ 3 0 D34 oe i l 8 Be a 2 8 8 DST DOS es DQS7 Wy DOS i DQS x VSS DM DM DQI 59 56 A DQ 3 0 D7 DQ 3 0 D25 wk 8 w 8 i Be 8 gt lll Vtt WwW Vppspp mr SPD VDD ae T ne DO D35 Vu i D0 D35 VREFCA A D0 D35 VREFDQ t D0 D35 Vss 2 s D0 D35 Note 1 DQ to I O wiring may be changed within a nibble 2 See wiring diagrams for all resistors values 3 ZQ pins of each SDRAM are connected to individual RZQ resistors 240 1 ohms Rev 1 0 Aug 2012
27. Min Max Min Max VIH DQ DC100 DC input logic high Vref 0 100 VDD Vref 0 100 VDD V 4 5 VIL DQ DC100 DC input logic low VSS Vref 0 100 VSS Vref 0 100 V 1 6 VIH DQ AC175 AC input logic high Vref 0 175 Note2 i V 1 2 7 VIL DQ AC175 AC input logic low Note2 Vref 0 175 V 1 2 8 VIH DQ AC150 AC Input logic high Vref 0 150 Note2 Vref 0 150 Note2 V 1 2 7 VIL DQ AC150 AC input logic low Note2 Vref 0 150 Note2 Vref 0 150 V 11 2 8 VIH CA AC135 AC input logic high mV 1 2 7 VIL CA AC135 AC input logic low i S mV 1 2 8 VRefDQ DC DD lu 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD V 3 4 Notes 1 Vref VrefDQ DC 2 Refer to Overshoot and Undershoot Specifications on page 40 3 The ac peak noise on Vner may not allow Ver to deviate from Vgerpo pc by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 VIH dc is used as a simplified symbol for VIH DQ DC100 6 VIL dc is used as a simplified symbol for VIL DQ DC100 7 VIH ac is used as simplified symbol for VIH DQ AC175 VIH DQ AC150 and VIH DQ AC135 VIH DQ AC175 value is used when Vref 0 175V is referenced VIH DQ AC150 value is used when Vref 0 150V is referenced and VIH DQ AC135 value is used when Vref 0 135V is referenced 8 VIL ac is used as simplified symbol for VIL DQ AC175 VIL DQ AC150 and VIL DQ AC135 VIL DQ AC175 value is used when Vref 0 17
28. RA VS W os VS Ws VSS pa SCH a 3 E g GR E g DO 3 0 D11 DQ 3 0 D10 DQ 3 0 D13 DQ 3 0 D42 v 82 92189 w 8 5 wile w 8 amp 91899 ww 8 5 E E Ly t e e RA A E VSS WY Sds NS pp En DOS S DOS S DOS S DOs S EE z DM z DM Z z DO 3 0 D13 DQ 3 0 D12 DQ 3 0 D41 Boel D40 S g w BI 8 w l8 w 5 95189 w 8 8 io 218 sis 8 5 E E La La La La e La DOs VS WI E imi VSS M SC S g ES g GR E g W DQ 3 0 D15 DQ 3 0 D14 i DQ 3 0 D39 3 DQ 3 0 D38 z S w 2188 sw 8 willie w 8 wile 8 io 218 g 8 5 La gt t La T e e RA Tan Bs VSS WY Das VSS pa SC MEn BM g EN g pas g M 00 3 0 D17 S DQ 3 0 D16 DQ 3 0 D37 SERT D36 E 8 8 8 8 w 2188 8 8 wikis s8 we 8 218 sw 8 5 F La Le e L La e A Rev 1 0 Aug 2012 22 S CP ix K 32GB 4Gx72 Module 4Rank of x4 page4 vss DQS13 DQS13 VSS DQ 39 36 vss DQS14 DQS14 VSS DQ 47 44 vss DQS15 DQS15 VSS DQ 55 52 vss DQS16 DQS16 vss DQ 63 60 VtE 31 Note
29. Units Notes Min Typ Max VDDQ supply Voltage for Output 1 425 1 500 1 575 1 2 Notes 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Rev 1 0 Aug 2012 26 SK ni AC amp DC Input Measurement Levels AC and DC Logic I nput Levels for Single Ended Signals AC and DC Input Levels for Single Ended Command and Address Signals Single Ended AC and DC I nput Levels for Command and ADDress DDR3 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max VIH CA DC100 DC input logic high Vref 0 100 VDD V 1 5 VIL CA DC100 DC input logic low VSS Vref 0 100 V 1 6 VIH CA AC175 AC input logic high Vref 0 175 Note2 V 1 2 7 VIL CA AC175 AC input logic low Note2 Vref 0 175 V 1 2 8 VIH CA AC150 AC Input logic high Vref 0 150 Note2 V 1 2 7 VIL CA AC150 AC input logic low Note2 Vref 0 150 V 1 2 8 VIH CA AC135 AC input logic high V 1 2 7 VIL CA AC135 AC input logic low V 1 2 8 VIH CA AC125 AC Input logic high V 1 2 7 VIL CA AC125 AC input logic low V 1 2 8 Vesna ins 0 49 VDD 0 51 VDD V 3 4 Notes 1 For input only pins except RESET Vref VrefCA DC 2 Refer to Overshoot and Undershoot Specifications on page 40 3 The ac peak noise on Vref may not allow Vner to deviate from Vgerca pc by more than 1 VDD for reference approx
30. Vrr Vppg 2 Differential AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Differential AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 1600 Voudift ac AC differential output high measurement level for output SR 0 2 x VDDQ V 1 VoLaiff Ac AC differential output low measurement level for output SR 0 2 x Vppq V 1 Notes 1 The swing of 0 2 x Vppq is based on approximately 50 of the static differential output high or low swing with a driver impedance of 40 9 and an effective test load of 25 Q to Vtr Vppo 2 at each of the differential outputs Rev 1 0 Aug 2012 36 SK ni Single Ended Output Slew Rate When the Reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo ac and Vouac for single ended signals are shown in table and figure below Single ended Output slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VOL AC VOH AC Voun acy VoL Ac l DeltaTRse Single ended output slew rate for falling edge VoH AC VoL AC Vou acy VoL Ac l DeltaTFse Notes 1 Output slew rate is verified by design and characterisation and may not be subject to production test Single Ended Output Voltage l e DQ VOL AC Delta TFse
31. 00 1 0 F 0 00110011 nRRD 2 D 1 0 0 0 0 1 00 0 0 F 0 ai repeat above D Command until 2 nRRD 1 2 2 nRRD repeat Sub Loop 0 but BA 2 0 2 3 3 nRRD repeat Sub Loop 1 but BA 2 0 3 4 4 nRRD D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW 1 if necessary 5 nFAW repeat Sub Loop 0 but BA 2 0 4 6 nFAW nRRD repeat Sub Loop 1 but BA 2 0 5 7 nFAW 2 nRRD repeat Sub Loop 0 but BA 2 0 6 8 nFAW 3 nRRD repeat Sub Loop 1 but BA 2 0 7 T 5 9 nFAW 4 nRRD D 1 0 0 0 0 7 00 0 0 F 0 X Assert and repeat above D Command until 2 nFAW 1 if necessary S 2 2 nFAW 0 ACT 0 0 1 1 0 0 00 0 0 F 0 e a 10 2 nFAW 1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 FEEDS Repeat above D Command until 2 nFAW nRRD 1 2 nFAW nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 11 2 nFAW nRRD 1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 ees Repeat above D Command until 2 nFAW 2 nRRD 1 12 2 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 2 13 2 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 3 D 1 0 0 0 0 3 00 0 0 0 0 By eon er nRRD Assert and repeat above D Command until 3 nFAW 1 if necessary 15 3 nFAW repeat Sub Loop 10 but BA 2 0 4 16 3 nFAW nRRD repeat Sub Loop 11 but BA 2 0 5 17 3 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 6 18 3 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 7 D 1 0 0 0 0 7 00 0 0 0 0 19 IER Assert and repeat above D Command until 4 nFAW 1 if n
32. 1 and CKI are NC Unused register inputs ODT1 and CKE1 have a 3302 resistor to ground Rev 1 0 Aug 2012 14 SK ni 8GB 1Gx72 Module 2Rank of x8 page1 lt lt 22 95 m lt 1 5 9 OE lt mim mamam o O oz miS d TITTEN TTE BESE y 8 zg g SES L DIE ISE KIR E zg H P HIS Z KKL g zg KNS Q DQS8 Wy DUS DQS DQS4 NN DUS DQS Do8 up ee wa ube s E E DM8 DQ0S17 W TDQS TDQS e DM4 DQS13 M TDQS TDQS 2 BOST M4TDQS D8 z Tos D17 E DOSIS WTbQS D4 E TE D13 Z CB 0 DQ 7 0 DQ 7 0 DQ 39 32 W DQ 7 0 DQ 7 0 20 9 e 20 e opgeet WELLLLLLL Meee MULITITIE E SEH mi a
33. 198 53 NC 19 DQ11 139 Vss 79 S2 NC 199 Vss 20 Vss 140 DQ20 80 Vss 200 DQ36 21 DQ16 141 DQ21 81 DQ32 201 DQ37 22 DQ17 142 Vss 82 DQ33 202 Vss 23 Vss 143 SEIL 83 Ver 203 x xm u WR a ma wo WEE 25 DQS2 145 Vss 85 DQS4 205 Vss 26 Vss 146 DQ22 86 Vss 206 DQ38 27 DQ18 147 DQ23 87 DQ34 207 DQ39 28 DQ19 148 Vss 88 DQ35 208 Vss 29 Vss 149 DQ28 89 Vss 209 DQ44 30 DQ24 150 DQ29 90 DQ40 210 DQ45 31 DQ25 151 Vss 91 DQ41 211 Vss NC No Connect RFU Reserved Future Use Rev 1 0 Aug 2012 SK CP ix pa s area zy S Panera du ete Gi Ex s isi o 32 Vss 152 ri 92 Vss 212 S 33 DQS3 153 E 93 DQS5 213 Es 34 DQS3 154 Vss 94 DQS5 214 Vss 35 Vss 155 DQ30 95 Vss 215 DQ46 36 DQ26 156 DQ31 96 DQ42 216 DQ47 37 DQ27 157 Vss 97 DQ43 217 Vss 38 Vss 158 CB4 NC 98 Vss 218 DQ52 39 CB0 NC 159 CB5 NC 99 DQ48 219 DQ53 40 CB1 NC 160 Vss 100 DQ49 220 Vss 41 Vss 161 ir d 101 Vss 221 RE 42 DQS8 162 aoe 102 DQS6 222 ots 43 DQS8 163 Vss 103 DQS6 223 Vss 44 Vss 164 CB6 NC 104 Ver 224 DQ54 45 CB2 NC 165 CB7 NC 105 DQ50 225 DQ55 46 CB3 NC 166 Vss 106 DQ51 226 Vss 47 Vss 167 NC TEST 107 Vss 227 DQ60 48 VTT NC 168 RESET 108 DQ56 228 DQ61 KEY KEY 109 DQ57 229 Vss 49 VTT NC 169 CKE1 NC 110 Vss 230 K 50 CKE0 170 VoD 111 DQS7 231 Ka 51 VoD 171 A15 112 DQS7 232 Vss 52 BA2 172 A14 113 Vss 233 DQ62
34. 3 V 1 2 Single ended high level for Ck CK VDD 2 0 175 Note 3 V 1 2 VSEL Single ended low level for strobes Note 3 VDD 2 0 175 V 1 2 Single ended low level for CK CK Note 3 VDD 2 0 175 V 1 2 Notes 1 For CK CK use VIH VIL ac of ADD CMD for strobes DOS DOS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs 2 VIH ac VIL ac for DQs is based on VREFDQ VIH ac VIL ac for ADD CMD is based on VREFCA if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 40 Rev 1 0 Aug 2012 33 SK yi Differential nput Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DQS DQS must meet the requirements in table below The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS WS E 4 f i X Vix d m d VSEH Cross point voltage for different
35. 4 3284 mA IDD3P 2028 2028 mA IDD4R 3644 4184 mA IDD4W 3644 4184 mA IDD5B 4634 4944 mA IDD6 1668 1668 mA IDD6ET 1812 1812 mA IDD7 4814 5354 mA Rev 1 0 Aug 2012 63 SK niy Module Dimensions 512Mx72 HMT451R7MFR8C Front P 133 35 gt 128 95 lt gt SDTS LL AN 2 10 0 15 4X3 00 0 10 EE Y 4 8 8 Detail A Q Detail B Detail C Y 2X3 00 0 10 LJ U WV 240 O Back 2x R0 75 Max Detail of Contacts A Detail of Contacts B 1 204 0 15 80 0 05 T lt 3 0 1 S n N 1 00 lt Note Detail of Contacts C N D e 3 403 0 15 2 50 0 20 E ere 50 0 d see P 5 00 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 0 Aug 2012 Side 3 43mm max n 1 274010mm Na ax Units millimeters 64 SK nix 1Gx72 HMT41GR7MFR4C Front P 133 35 128 95 lt gt p 2 10 0 15 SIDE A Detail A OD a E k c mds SS t E 9 8 dco ml i e Detail B Detail C v Back
36. 40 D42 S D28 D30 D32 D34 S D54 D56 D58 D60 BA N 0 A L ARBA N 0 A gt BA N 0 SDRAMs D 9 0 D 27 18 _ BA N 0 A I L BRBA N 0 A BA N 0 SDRAMs D 53 44 D 71 62 T ARBAIN 0 B BAIN SDRAM DIT TU D35281 T BRBAIN 018 BANO SDRAMs Die EE A N 0 J L ARA N 0 A gt A N 0 SDRAMs D 9 0 D 27 A N 0 A ram 0 A gt A N 0 SDRAMs D 55 44 D 71 62 N 0 S ARAIN 0 B gt AN 0 SDRAMs D 17 a EE L N 0 P RAIN 0 B gt A NU SDRAMs p GERS RAS MA L ARRASA RAS SDRAMs D 9 0 D 27 18 RAS Ad L BRRASA gt RAS SDRAMs D 53 44 D 71 62 ARRASB gt RAS SDRAMs D 17 10 D 35 28 BRRASB RAS SDRAMs D 43 36 D 61 54 CAS wr P ARCASA gt GAS SDRAMs D 9 0 D 27 18 CAS wr P BRCASA GAS SDRAMs D 53 44 D 71 62 L ARCASB CAS SDRAMs D 17 10 D 35 28 L BRCASB CAS SDRAMs D 43 36 D 61 54 WE L FARWEA WE SDRAMs D 9 0 D 27 18 WE L BRWEA WE SDRAMs D 53 44 D 71 62 ARWEB WE SDRAMs D 17 10 D 35 28 BRWEB WE SDRAMs D 43 36 D 61 54 CKE0 y A ARCKEOA gt CKE1 SDRAMs D1 D3 D5 D7 D9 CKE0 B L BRCKEQA gt CKEI SDRAMs D45 D47 D49 D51 D53 D19 D21 D23 D25 D27 D63 D65 D67 D69 D71 ARCKEOB gt CKE1 SDRAMs D11 D13 D15 D17 BRCKEOB gt CKE1 SDRAMs D37 D39 D41 D43 D29 D31 D33 D35 D55 D57 D59 D61 CKE1 L ARCKE1A gt CKE0 SDRAMs D0 D2 D4 D6 D8 CKEL BRCKE1A CKE0 SDRAMs D44 D46 D48 D50 D52 D18 D20 D22 D24 D26 D
37. 5V is referenced VIL DQ AC150 value is used when Vref 0 150V is referenced and VIL DQ AC135 value is used when Vref 0 135V is referenced Rev 1 0 Aug 2012 28 SK yi Vref Tolerances The dc tolerance limits and ac noise limits for the reference voltages vnerca and Vnerpq are illustrated in figure below It shows a valid reference voltage Vnesi t as a function of time per stands for VpercA and Vnetpo likewise Vref DC is the linear average of Vner t over a very long period of time e g 1 sec This average has to meet the min max requirements in the table Differential Input Slew Rate Definition on page 35 Further more Vref t may temporarily deviate from Vger pc by no more than 1 VDD voltage VDD Vner t Ver ac noise Ret VRef DC max VDD 2 VRef DC min VRef DC Illustration of Vperpc tolerance and Vref ac noise limits The voltage levels for setup and hold time measurements Viu ac Viu pc Vit Ac and Vii pc are depen dent on Vger Vner shall be understood as Vger pc as defined in figure above This clarifies that dc variations of Vger affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for Vger pc deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold speci
38. 62 D64 D66 D68 D70 ARCKE1B CKE0 SDRAMs D10 D12 D14 D16 BRCKE1B CKE0 SDRAMs D36 D38 D40 D42 D28 D30 D32 D34 D54 D56 D58 D60 OUT L ARODTOA ODTI SDRAMs D1 D3 D5 D7 D9 ODT1 WU L BRODT1A ODT1 SDRAMs D45 D47 D49 D51 D53 _ D19 D21 D23 D25 D27 D63 D65 D67 D69 D71 ARODTOB ODTO SDRAMs D11 D13 D15 D17 BRODT1B ODTO SDRAMs D37 D39 D41 D43 D29 D31 D33 D35 D55 D57 D59 D61 CKO APCKOA gt CK SDRAMs D 9 0 CKO BPCKOA gt CK SDRAMs D 53 44 1209 APCKOB CK SDRAMs D 17 10 1209 BPCKOB CK SDRAMs D 43 36 z 459 APCK1A gt CK SDRAMs D 27 18 459 BPCK1A CK SDRAMs D 71 62 m CET APCK1B gt CK SDRAMs D 35 28 a d BPCK1B CK SDRAMs D 61 54 CKO APCKOA CK SDRAMs D 9 0 CKO BPCK0A gt CK SDRAMs D 53 44 APCKOB CK SDRAMs D 17 10 BPCKOB CK SDRAMs D 43 36 APCK1A gt CK SDRAMs D 27 18 BPCK1A gt CK SDRAMs D 71 62 APCK1B CK SDRAMs D 35 28 BPCK1B CK SDRAMs D 61 54 PAR IN w Err Out PAR IN W Err Out BRESET RST RESET J RST RST SDRAMs D 35 0 CK1 1202 5 1 CKO and CKO are differentially terminated with a single 120 Ohms 5 resistor 2 CK1 and CK1 are differentially terminated with a single 120 Ohms 3 Unused register inputs ODT1 for Register A and ODTO for Register B are tied to ground 4 The module drawing on this page is not drawn to scale Rev 1 0 Aug 2012 t5 resistor but is not used 24 SK ni Absolute Maximum Ratings Absolute Ma
39. AM DD 0 D8 VDDSPD VDDSPD SAO SAU Qu RCASA gt CAS SDRAMs D 3 0 D8 EVENT EVENT SPD with SAL SA1 MP S RCASA gt CAS SDRAMs D 7 4 WE ir RWEA WE SDRAMs D 3 0 D scL scL Integrated sa A7 RWEA WE SDRAMs D 7 4 TS CKEO E RCKE0A CKE0 SDRAMs D 3 0 D8 SDA SDA VSS VSS R RCKEOB gt CKE0 SDRAMs D 7 4 ODTO VV RODTOA ODTO6 SDRAMs D 3 0 D8 Plan to use SPD with Integrated TS of Class B and RODTOB gt ODTO SDRAMs D 7 4 S CK0 P L cka CK po might be changed on customer s requests For more noo L PCKOB os S 5 SCH ve details of SPD and Thermal sensor please contact oo DCH E s D 7 4 i hra CKO L PCKOA CK SDRAMs D 3 0 D8 local SK hynix sales representative CKO sme PCKOB CK SDRAMs D 7 4 CKO t1 PAR IN M OERRF Err Out RESET RST m RST SDRAMs D 8 0 S 3 2 CKE1 ODT1 are NC Unused register inputs ODT1 and CKE1 have a 3302 resistor to ground Rev 1 0 Aug 2012 12 SK nix 8GB 1Gx72 Module 1Rank of x4 pagel vss WI vss vss WwW as 2 lt i d E 20 Sle 81589 2s UE e z CIK L s Lll I lI l 1 Li Doss w pQS ZO DOS N DS z DQS8
40. BRESET RST RST SDRAMs D 35 0 S 3 2 CK1 and CK1 are NC Rev 1 0 Aug 2012 S CP ix K 32GB 4Gx72 Module 4Rank of x4 pagel vss DQS8 DQS8 VSS CB 3 0 vss DQS3 DQS3 vss DQ 27 24 vss DQS2 DQS2 DQ 19 16 vss DQS1 DQS1 DQ 11 8 vss DQS0 DQS0 DQ 3 0 Vtt B lt lt o ER lt PT oz 3 4 8 i 2 O 3 si 883052 s T sEBSESBEE 25 unis g 28 Delgo 2 g d iR i 9444441 i i l L L Ii ZW bas VS W os Minim ids M55 WIES B4 S E 3 GR g E g DO 3 0 D9 DQ 3 0 D8 DQ 3 0 D45 DQ 3 0 D44 S DOERNER wie w 8 5 we
41. D64 E 8 w ie w 5 w BBE 8 5 E La zQ ZQ nos Dos 5 z DQ 3 0 D67 DQ 3 0 D66 z 3 g DEIER io 218 g 8 5 E La Le zQ ZQ Dos Dos Ce 5 DQ 3 0 D69 3 DQ 3 0 D68 E 8 wile 8 io 218 1g 8 5 EE e e ZQ ZQ pos Dos E E D Fram 2A DQ 3 0 K E we w 5 io 218 sb 5 e I e Le Rev 1 0 Aug 2012 21 S CP ix K 32GB 4Gx72 Module 4Rank of x4 page3 vss DQS4 DQS4 DQ 35 32 vss DQS5 DQS5 DQ 43 40 vss DQS6 DQS6 DQ 51 48 vss DQS7 DQS7 vss DQ 59 56 VtE 31 n a af 26 5555 2S g eG RIESE i 8 l a N x m HHE 28 BIN d ES i 94404441 i d l l l L
42. DHS HMT451R7MFR8C G7 H9 PB 4GB 512Mx72 512Mx8 H5TQ4G83MFR 9 1 X HMT41GR7MFR8C G7 H9 PB 8GB 1Gx72 512Mx8 H5TQ4G83MFR 18 2 X HMT41GR7MFR4C G7 H9 PB 8GB 1Gx72 1Gx4 H5TQ4G43MFR 18 1 X HMT42GR7MFR4C G7 H9 PB 16GB 26x72 1Gx4 H5TQ4G43MFR 36 2 O HMT84GR7MMR4C G7 H9 32GB 4Gx72 DDP 2Gx4 H5TQ8G43MMR 36 4 O Rev 1 0 Aug 2012 n order to uninstall FDHS please contact sales administrator SK nix Key Parameters CAS RAS MT s Grade E Latency rice oan ERE CL tRCD tRP ns ns ns ns ns tCK DDR3 1066 G7 1 875 7 13 125 13 125 37 5 50 625 7 7 7 13 5 13 5 49 5 DDR3 1333 H9 1 5 9 13 125 13 125 39 49 125 9 9 9 13 75 13 75 48 75 DDR3 1600 PB 1 25 11 13 125 13 125 35 48 125 11 11 11 SK hynix DRAM devices support optional downbinning to CL9 and CL7 SPD setting is programmed to match Speed Grade Frequency MHz Grade Remark CL6 CL7 CL8 CL9 CL10 CL11 G7 800 1066 1066 H9 800 1066 1066 1333 1333 PB 800 1066 1066 1333 1333 1600 Address Table 4GB 1Rx8 8GB 1Rx4 8GB 2Rx8 16GB 2Rx4 32GB 4Rx4 Refresh Method 8K 64ms 8K 64ms 8K 64ms 8K 64ms 8K 64ms Row Address A0 A15 A0 A15 A0 A15 A0 A15 A0 A15 Column Address A0 A9 A0 A9 A11 A0 A9 A0 A9 A11 A0 A9 A11 Bank Address BAO BA2 BAO BA2 BAO BA2 BAO BA2 BAO BA2 Page Size 1KB 1KB 1KB 1KB 1KB Rev 1 0 Aug 2012
43. DOS D DOSU ABC vss pM 2 vss DM z CB 3 0 A DQ 3 0 D8 H Al AADQ 13 01 D17 S z z 2 o o plssissssE 3 28 w 8 5 La L La DQS3 d DOS za DQS12 dd DOS zQ Doss DOS lt Dos wypas vss om z vss DM z DQ 27 243 A DQ 3 0 D3 H DQ 31 28FA DQ 3 0 D12 2 2 o o we 3 218 12 8 5 4 La e e DQS2 w pos 70 posi DS um Dasz POS D Dos wypos 3 DM Z vss pM z DQ 19 16M DQ 3 0 D2 H Dpo23 20 A DO 13 01 D11 z 2 u 0 218 g RIRE Big p BIS RKE Ble L Ls e 1 e DQS1 dd DOS za DQS10 DOS zQ DOSI DOS DQS10 7w DOS DM DQL11 8 W DQ 3 0 D1 A O N BALO N i w 5 I VSS DM DOLL Lal DQ 3 0 D10 w Rls sss vss y Ts vss peso oel pos ZO h poss lp 20 vs ier z vs om S DQ 3 0 dvl DQ 3 0 DO S DQI7 4 df DQ 3 0 D9 3 wie se 0595 x 8 BIR Vtt wv VDDSPD VDDSPD SAO DAD EVENT 4 EVENT SPD with SAL SA1 sCL SEL Integrated s42 sai SDA SDA TS VSS VSS Note 1 DQ to 1 O wiring may be changed within a nibble 2 Unless otherwise noted resistor values are 15 5 vss
44. DRAMs D 7 4 PCK1A gt CK SDRAMs D 12 9 D17 PCK1B CK SDRAMs D 16 13 PCKOA CK SDRAMs D 3 0 D8 PCKOB CK SDRAMs D 7 4 PCK1A gt CK SDRAMs D 12 9 D17 PCK1B gt CK SDRAMs D 16 13 12 8 D17 16 13 Sg ES 2 D 16 EA 8 D17 Err_Out RST SDRAMs D 17 0 S 3 2 CK1 and CK1 are NC Rev 1 0 Aug 2012 16 SK ni 16GB 2Gx72 Module 2Rank of x4 page1 lt lt z lt 9 3 44 SIBI dii EIE agg lt H VIS z 2 1 Lig p 1 IL opo ob DQS17 WY Dos pos DQS17 W DQS on DQS vss DM M s CB 7 4 DQ 3 0 D17 DQ 3 0 D35 3 3 0 BB g 8 5 DEIER DQs12 W DQS DQ512 W DOS VSS DM DQ 31 28 A DQ 3 0 D12 we s B t Dos DOS DQ 13 01 D30 w Rls 8 5 A N O BA N O A N O BA N O DQS11 A DOS DQSII W DOS VsS pM DQI23 20 A DQ 3 0 D11 we sb DOS DOS DM DQ 3 0 D29 A N O BALN O A N O BALN O w BIE sss DQS10 DOS DQS10 DOS VSS DM DQL15 12 A9 DQ 3 0 D10 wesw 8 Dos DQS DQ 3 0 D28 A N O BALN O A N O BALN O DODERER DQS0 A DQS DQS0 wW DOS VSS DM DQ 3 0 A9 DQ 3 0 DO we
45. IMM temperature is monitored by integrated thermal sensor The integrated thermal sensor comply with JEDEC TSE2002av Serial Presence Detect with Temperature Sensor Connection of Thermal Sensor SA0 S SPD with sA1 SCL Integrated c SDA TS Temperature to Digital Conversion Performance Parameter Condition Min Typ Max Unit Active Range 75 C lt Ty lt 95 C Temperature Sensor Accuracy Grade B Monitor Range I 40 C lt Ty lt 125 C E EE E 20 C lt T4 lt 125 C 2 0 3 0 C Resolution 0 25 RS Rev 1 0 Aug 2012 11 S de Functional Block Diagram 4GB 512Mx72 Module 1Rank of x8 a gg 0 og 20 THEE TEHE Bele leg 8 28 FAHER l l l l l l l l l l l l l l l DQS8 V DOS ZQ DQS4 V DDS ZQ DQS8 W DOS E DQS4 m DOS E DM8 DQS17 W TDQS o JL DM4 DQS13 A TDQS z L DOS M TDOS D8 DQ w Tbs D4 CB 0 W DQ 7 0 ES DQ 39 32 W DQ 7 0 S o 2 2 lise xe 8 lise 8 LIIILLLLI Seana ae DQS3 WDQS ZQ DQS5 W DQS ZQ DQS3 wW DOS d DQS5 N DOS SS DM3 DQS12 W4 TDQS o DM5 DQS14 A TDQS o L DQS12 W TDQS D3 2 Du w TDQS D5 E DQ 31 24
46. OHdiff AC for differential signals as shown in table and figure below Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VoLaiff AC Vonaitt Ac Vouaitt AC VoLaitr c Delta Pdf Differential output slew rate for falling edge Vouditt AC VoLaitt ac Vouditt AC Mota acy Delta TFdiff Notes 1 Output slew rate is verified by design and characterization and may not be subject to production test Differential Output Voltage i e DQS DQS M vOHdiff AC DN vOLdiff AC Differential Output Slew Rate Definition Differential Output slew Rate Definition Differential Output Slew Rate DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 Unit nits Parameter Symbol Min Max Min Max Min Max Min Max Differential Output Slew Rate SRQdiff 5 10 5 10 5 10 5 10 V ns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Rev 1 0 Aug 2012 38 SK yi Reference Load for AC Timing and Output Slew Rate Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements It is not intended as a precise representation of any particular syste
47. RO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT Nom enable set MR1 A 9 6 2 011B RTT Wr enable set MR2 A 10 9 10B c Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 OB to disable or 1B to enable feature e Self Refresh Temperature Range SRT set MR2 A7 OB for normal or 1B for extended temperature range f Read Burst Type Nibble Sequential set MRO A 3 0B Rev 1 0 Aug 2012 54 SK ni Table 3 IDD0 Measurement Loop Pattern L 8 9 E 8 um e K mS o BZ BE iUi BS 3 3 pa 0 0 AT O O 1 1 0 0 00 0 0 1 2 DD 1 0 0 0 0 0 0 O 0 3 4 DD 1 1 1 1J J010 0 0 Oo ET repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 ii repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 O 1 1 0 0 00 0 0 F 0 1 nRC 1 2 DD 1 0 0 0 0 0 00 0 0 F 0 p 9 1 nRC 3 4 IDD 1 1 1 1 0 0 0 0 0 F o D m repeat pattern 1 4 until 1 nRC nRAS 1 truncate if necessary 988 IMRCenRAS PRE 0 0 1 0 O o 0 0 O E 0 sek repeat pattern 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8
48. SKE ni red DIMM DDR3 SDRAM Registered DI MM Based on 4Gb M die HMT451R7MFR8C HMT41GR7MFR8C HMT41GR7MFR4C HMT42GR7MFR4C HMT84GR7MMR4C SK hynix reserves the right to change products or specifications without notice Rev 1 0 Aug 2012 1 SK ni Revision History Revision No History Draft Date Remark 0 1 Initial Release Aug 2011 1 0 Latest JEDEC Spec and Product Line up Updated Aug 2012 Rev 1 0 Aug 2012 Ds SK hynix Description SK hynix Registered DDR3 SDRAM DIMMs Registered Double Data Rate Synchronous DRAM Dual In Line Memory Modules are low power high speed operation memory modules that use DDR3 SDRAM devices These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations Features Power Supply VDD 1 5V 1 425V to 1 575V VDDQ 1 5V 1 425V to 1 575V VDDSPD 3 0V to 3 6V Functionality and operations comply with the DDR3 SDRAM datasheet 8 internal banks Data transfer rates PC3 14900 PC3 12800 PC3 10600 PC3 8500 Bi Directional Differential Data Strobe 8 bit pre fetch Burst Length BL switch on the fly BL8 or BC4 Burst Chop Supports ECC error correction and detection On Die Termination ODT Temperature sensor with integrated SPD This product is in compliance with the RoHS directive Ordering Information Part Number Density Organization Component Composition aoe F
49. T DQ33 pos DOS D055 vE DoS EE SE S E o San AN Ws 2 S TDQS TDQS GS w TDQS D3 TE D12 DOH vT D5 Toe D14 E DQ 31 24 M DQ 7 0 DQ 7 0 DQ 47 40 M DQ 7 0 DQ 7 0 20 Q EN ZQ 20 o u Ege swe 2 RRR nn 2 Tobe ve bs wHBEsubb T ll T posz MWMDOS DQS Dase A Dos el EXE g m S An t o d 5 TDQS S TDQS DQSli MMTDOS D2 ES D11 E DQSi5 W TDQS D6 7 The D15 Z DQ 23 16 MM DQ 7 0 m DQ 7 0 DQ55 48 M DQ 7 0 E DQ 7 0 o o o a Perese MERE ewes eBgssuBBE TORR e s 655 2 I F N e Le en SE 5 n S eh SC S ke g DOSI TDS D1 Z ve D10 Z DS ToS D7 kee D16 B DQ 15 8 M DQ 7 0 DQ 7 0 2 DQ 63 56 M DQ 7 0 DQ 7 0 2 2 2 MOETE Jia BB vw 88S Mee MOTE t i t Doso w Dos DOS vt DQSO RA 5 DOS DM0 DQS9 TDQS S TDQS SZ Aeon TT POLL H DQ 7 0 K DQ 7 0 L E zB 5 9 MOTTE Rat vi I VDDSPD VDDSPD SAO SAO T EVENT EVENT SPD with SA1 SA1 is VS SCL J SCL Gees SA2 SM SDA SDA VSS L VSS Plan to use SPD with Integrated TS of Class B and Note might be changed on customer s requests For more 1 DQ to 1 O wiring may be changed within a byte 2 Unless otherwise noted resistor values are 15 Q 5 3 ZQ resistors are 240 Q 1 For all other resistor values refer to the appropriate wiring diagram 4 See the wiring diagrams for all resistor
50. aller JEDEC standard tCK AVG value 3 0 2 5 1 875 1 5 or 1 25 ns when calculat ing CL nCK tAA ns tCK AVG ns rounding up to the next Supported CL where tCK AVG 3 0 ns should only be used for CL 5 calculation tCK AVG MAX limits Calculate tCK AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED Reserved settings are not allowed User must program a different value Optional settings allow certain devices in the industry to support this setting however it is not a man datory feature Refer to DIMM data sheet and or the DIMM SPD information if and how this setting is supported Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization DDR3 SDRAM devices supporting optional down binning to CL 7 and CL 9 and tAA tRCD tRP must be 13 125 ns or lower SPD setti
51. ble 4 Rev 1 0 Aug 2012 51 Ds SK hynix Symbol Description Ipp2N Precharge Standby Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 pp2NnT Precharge Standby ODT Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 6 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal toggling according to Table 6 Pattern Details see Table 6 pp2P0 Precharge Power Down Current Slow Exit CKE Low External clock On CK CL see Table 1 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Ipp2p1 Precharge Power Down Current Fast Exit CKE Low External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL
52. ble 7 Data IO seamless read data burst with different DD4R data between one burst and the next one according to Table 7 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 7 Operating Burst Write Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS High between WR Command Address Bank Address Inputs partially toggling according to Table 8 Data IO seamless read data burst with different DD4W data between one burst and the next one according to Table 8 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 8 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at HIGH Pattern Details see Table 8 Burst Refresh Current CKE High External clock On CK CL nRFC see Table 1 BL 88 AL 0 CS High between REF Command IppsB Address Bank Address Inputs partially toggling according to Table 9 Data IO MID LEVEL DM stable at 0 Bank Activity REF command every nREF see Table 9 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 9 Self Refresh Current Normal Temperature Range Tease 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Tope Low Ex
53. ecessary a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Aug 2012 60 SK ni IDD Specifications Tcase 0 to 95 C Module IDD values in the datasheet are only a calculation based on the component IDD spec and register power The actual measurements may vary according to DQ loading cap 4GB 512M x 72 R DIMM HMT451R7MFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDD0 1169 1214 1214 mA IDD1 1259 1304 1304 mA IDD2N 989 1034 1034 mA IDD2NT 1034 1079 1079 mA IDD2P0 408 408 408 mA IDD2P1 426 426 426 mA IDD2Q 989 1034 1034 mA IDD3N 1079 1079 1079 mA IDD3P 453 453 453 mA IDD4R 1619 1754 1889 mA IDD4W 1664 1799 1934 mA IDD5B 2024 2069 2069 mA IDD6 408 408 408 mA IDD6ET 426 426 426 mA IDD7 2204 2339 2384 mA 8GB 1G x 72 R DI MM HMT41GR7MFR4C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 1574 1664 1664 mA IDD1 1754 1844 1844 mA IDD2N 1214 1304 1304 mA IDD2NT 1304 1394 1394 mA IDD2P0 588 588 588 mA IDD2P1 624 624 624 mA IDD2Q 1214 1304 1304 mA IDD3N 1394 1394 1394 mA IDD3P 678 678 678 mA IDD4R 2294 2564 2834 mA IDD4W 2294 2564 2744 mA IDD5B 3284 3374 3374 mA IDD6 588 588 588 mA
54. ential input slew rate for rising edge CK CK and DOS DOS oe Vigitmax ViHdif min ViHaittmin ViLdittmax DeltaT Rdiff Differential input slew rate for falling edge CK CK and DQS DOS SET Vindiftmin ViLdifmax ViHdiffmin V ILaiftmax Delta TFdiff Notes The differential signal i e CK CK and DQS DQS must be linear between these thresholds Differential Input Voltage i e DQS DQS CK CK EE EE VHdiffrin B ViLdiffmax Differential Input Slew Rate Definition for DQS DQS and CK CK Rev 1 0 Aug 2012 35 SK nix AC amp DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Single ended AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 1600 VoH DC DC output high measurement level for IV curve linearity 0 8 x VDDQ V VOM DC DC output mid measurement level for IV curve linearity 0 5 x Vppq V VoL DO DC output low measurement level for IV curve linearity 0 2 x Vppq V VoH AC AC output high measurement level for output SR Vrr 0 1 x Vppo V 1 VoL AC AC output low measurement level for output SR Vrr 0 1 x Vppo V 1 Notes 1 The swing of 0 1 x Vppo is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 40 9 and an effective test load of 25 to
55. fication and derating values need to include time and voltage associated with Vperac noise Timing and voltage effects due to ac noise on Vp up to the speci fied limit 196 of VDD are included in DRAM timings and their associated deratings Rev 1 0 Aug 2012 29 SK ni AC and DC Logic I nput Levels for Differential Signals Differential signal definition VILDIFFACMIN 210 Of I fee O O oe Stee cd WIEBIFENIN 222 o u a ee ccce Ln tt Bl as ce at bala half cycle mr ose tee eteseee ses Differential Input Voltage i e DQS DQS CK CK VILDIFRACMAX emm eee eee N Foe ee cc sss I Definition of differential ac swing and time above ac level tpvac Rev 1 0 Aug 2012 30 SK ni Differential swing requirements for clock CK CK and strobe DQS DQS Differential AC and DC I nput Levels DDR3 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max VIHdiff Differential input high 0 180 Note 3 V 1 VILdiff Differential input logic low Note 3 0 180 V 1 VIHdiff ac Differential input high ac 2 x VIH ac Vref Note 3 V 2 VILdiff ac Differential input low ac Note 3 2 x VIL ac Vref V 2 Notes 1 Used to define a differential signal slew rate 2 For CK CK use VIH VIL ac of AADD CMD and VREFCA for DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs and VREFDQ if a reduced ac high or ac low levels is used for a signal g
56. he Err Out Address and Control bus Rev 1 0 Aug 2012 5 SK ni Input Output Functional Descriptions Symbol Type Polarity Function CKO IN Positive Positive line of the differential pair of system clock inputs that drives input to the on Line DIMM Clock Driver CKO IN Negative Negative line of the differential pair of system clock inputs that drives the input to the Line on DIMM Clock Driver CK1 IN id Terminated but not used on RDIMMs CK1 IN i e Terminated but not used on RDIMMs CKE HIGH activates and CKE LOW deactivates internal clock signals and device input CKE 1 0 IN Active buffers and output drivers of the SDRAMs Taking CKE LOW provides PRECHARGE i High POWER DOWN and SELF REFRESH operation all banks idle or ACTIVE POWER DOWN row ACTIVE in any bank Enables the command decoders for the associated rank of SDRAM when low and dis ables decoders when high When decoders are disabled new commands are ignored ST3 0 IN Active and previous operations continue Other combinations of these input signals perform Low unique functions including disabling all outputs except CKE and ODT of the register s on the DIMM or accessing internal control words in the register device s For modules with two registers S 3 2 operate similarly to S 1 0 for the second set of register out puts or register control words ODT 1 0 IN du On Die Termination control s
57. ial input signals CK DQS Vix Definition CK DQS CK DQS DDR3 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max VCK Differential Input Cross Point Voltage 150 150 mV 2 IX relative to VDD 2 for CK CK 175 175 mV 1 Differential Input Cross Point Voltage _ Ree relative to VDD 2 for DOS DAS Ka 5 me 2 Notes 1 Extended range for Vy is only allowed for clock and if single ended clock input signals CK and CK are monotonic with a single ended swing VSEL VSEH of at least VDD 2 250 mV and when the differential slew rate of CK CK is larger than 3 V ns 2 The relation between Vix Min Max and VSEL VSEH should satisfy following VDD 2 Vix Min VSEL gt 25mV VSEH VDD 2 Vix Max gt 25mV Rev 1 0 Aug 2012 34 SK ni Slew Rate Definitions for Single Ended I nput Signals See 7 5 Address Command Setup Hold and Derating on DDR3 Device Operation for single ended slew rate definitions for address and command signals See 7 6 Data Setup Hold and Slew Rate Derating on DDR3 Device Operation for single ended slew rate definition for data signals Slew Rate Definitions for Differential nput Signals Input slew rate for differential signals CK CK and DQS DQS are defined and measured as shown in table and figure below Differential Input Slew Rate Definition Measured Description E Defined by Min ax Differ
58. ignals RAS CAS WE IN Active When sampled at the positive rising edge of the clock CAS RAS and WE define the I Low operation to be executed by the SDRAM VREFDQ Supply Reference voltage for DQ0 DQ63 and CB0 CB7 V Suppl Reference voltage for A0 A15 BA0 BA2 RAS CAS WE S0 S1 CKE0 CKE1 Par_In REFCA pp y ODTO and ODT1 Selects which SDRAM bank of eight is activated BA 2 0 IN _ BAO BA2 define to which bank an Active Read Write or Precharge command is being applied Bank address also determines mode register is to be accessed during an MRS cycle Provided the row address for Active commands and the column address and Auto Precharge bit for Read Write commands to select one location out of the mem A 15 13 ory array in the respective bank A10 is sampled during a Precharge command to deter 12 BC 11 IN mine whether the Precharge applies to one bank A10 LOW or all banks A10 HIGH If 10 AP 9 0 only one bank is to be precharged the bank is selected by BA A12 is also utilized for BL 4 8 identification for BL on the fly during CAS command The address inputs also pro vide the op code during Mode Register Set commands DQ 63 0 CB 7 0 1 0 Data and Check Bit Input Output pins Active c s T DM 8 0 IN High Masks write data when high issued concurrently with input data Vpp Vss Supply Power and ground for the DDR SDRAM input buffers and core logic Vit Supply Termination Voltage for Address Command Control Clock nets
59. m environment or a depiction of the actual load presented by a production tester System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment Manufacturers correlate to their production test conditions generally one or more coaxial transmission lines terminated at the tester electronics VDDQ VIT VDDQ 2 Reference Load for AC Timing and Output Slew Rate Rev 1 0 Aug 2012 39 SK ni Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Address and Control Pins DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 67 0 5 0 4 0 33 V ns Maximum undershoot area below VSS See Figure below 0 67 0 5 0 4 0 33 V ns A0 A15 BAO BA3 CS RAS CAS WE CKE ODT See figure below for each parameter definition Maximum Amplitude Overshoot Area VDD Volts V vss Undershoot Area Maximum Amplitude Time ns Address and Control Overshoot and Undershoot Definition Rev 1 0 Aug 2012 40 SK ni Clock Data Strobe and Mask Overshoot and Undershoot Specifications AC Over
60. ment conditions please refer to the J EDEC document J ESD51 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported Dur ing operation the DRAM case temperature must be maintained between 0 85 C under all operating conditions Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 A6 0b and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 0b DDR3 SDRAMs support Auto Self Refresh and in Extended Temperature Range and please refer to component datasheet and or the DIMM SPD for tREFI requirements in the Extended Temperature Range Rev 1 0 Aug 2012 25 SK ni AC amp DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Rating Symbol Parameter
61. nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL 55 Rev 1 0 Aug 2012 De SK hynix Table 4 IDD1 Measurement Loop Pattern S S z S F a lt e Gaz 3 Pils 8 8 S 3 3 3 amp ve 3 OS lt lt lt lt lt 0 O ACT 0 O 1 1 0 0 0 0 0 0 1 2 DD 1 0 0 0 0 0 0 0 0 0 3 4 DD 1 1 1 1 0 010 0 0 0 ws repeat pattern 1 4 until nRCD 1 truncate if necessary nRCD RD 0 1 O 1 0 0 0 0 O 0 0 00000000 m repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 O 1 0 0 0 0 0 O 0 0 D repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT O O 1 1 0 0 0 O 0 F 0 1 nRC 1 2 DD 1 O 0 0 0 0 0 0 0 F 0 2 1 nRC 3 4 IDD 1 1 1 1 0 0 l olololFfF o E ds repeat pattern nRC 1 4 until nRC nRCE 1 truncate if necessary 8 L 1 nRC nRCD RD 0 1 O 1 0 0 0 0 0 F 0 00110011 us repeat pattern nRC 1 4 until nRC nRAS 1 truncate if necessary 1 nRC nRAS PRE 0 O 1 0 0 0 0 0 0 F 0 Er repeat pattern nRC 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0
62. ngs must be programmed to match For example DDR3 1333H devices supporting down binning to DDR3 1066F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600K devices supporting down binning to DDR3 1333H or DDR3 1600F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36 ns 13 125 ns for DDR3 1333H and 48 125ns tRASmin tRPmin 35 ns 13 125 ns for DDR3 1600K Rev 1 0 Aug 2012 47 SK yi Environmental Parameters Symbol Parameter Rating Units Notes Topr Operating temperature See Note 3 Hopr Operating humidity relative 10 to 90 96 1 TsrG Storage temperature 50 to 100 oc 1 Herc Storage humidity without condensation 5 to 95 K 1 PBAR Barometric Pressure operating amp storage 105 to 69 K Pascal 12 Note 1 Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Expousure to absolute maximum rating conditions for extended periods may affect reliablility 2 Up to 9850 ft 3 The designer must meet the case temperature specifications for individual module components Rev 1 0 Aug 2012 48 SK yi
63. ommand period 48 125 gt 9 BR dich eal tras 35 9 tREFI ns CWL 5 ICK AVG 2 5 3 3 ns 1 2 3 8 CL26 CWL 6 amp xave Reserved ns 1 2 3 4 8 CWL 7 lck AVG Reserved ns 4 CWL 5 awe Reserved ns 4 1 875 lt 2 5 CL 7 CWL 6 IcK AVG Optional ns 1 2 3 4 8 CWL 7 awe Reserved ns 1 2 3 4 8 CWL 8 awe Reserved ns 4 CWL 5 awe Reserved ns 4 CL 8 CWL 6 ICK AVG 1 875 2 5 ns 1 2 3 8 CWL 7 IcK AVG Reserved ns 1 2 3 4 8 CWL 8 aver Reserved ns 1 2 3 4 CWL 5 6 amp x ave Reserved ns 4 CL29 CWL 7 lck AVG ES SENE ns 1 2 3 4 8 Optional CWL 8 aver Reserved ns 1 2 3 4 CWL 5 6 amp xave Reserved ns 4 CL 10 CWL 7 IcK AVG 1 5 lt 1 875 ns 1 2 3 8 CWL 8 aver Reserved ns 1 2 3 4 cL 11 ENL 5 6 7 aval Reserved ns 4 CWL 8 lck AVG 1 25 1 5 ns 1 2 3 Supported CL Settings 5 6 7 8 9 10 11 ck Supported CWL Settings 5 6 7 8 lick Rev 1 0 Aug 2012 46 CH SK hynix Speed Bin Table Notes Absolute Specification ToPER Vppq Vpp 1 5V 0 075 V 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When mak ing a selection of tCK AVG both need to be fulfilled Requirements from CL setting as well as require ments from CWL setting tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchro nized by the DLL all possible intermediate frequencies may not be guaranteed An application should use the next sm
64. pin on TS SPD part No pull up resister is provided on DI MM V Suppl Serial EEPROM positive power supply wired to a separate power pin at the connector DDSPD HDN which supports from 3 0 Volt to 3 6 Volt nominal 3 3V operation The RESET pin is connected to the RESET pin on the register and to the RESET pin on RESET IN the DRAM Par In IN Parity bit for the Address and Control bus 1 Odd 0 Even Er Out OUT Parity error detected on the Address and Control bus A resistor may be connected from in ezer Err_Out bus line to Vpp on the system planar to act as a pull up TEST Used by memory bus analysis tools unused NC on memory DIMMs Rev 1 0 Aug 2012 SK ni Pin Assignments ELS ERE SC doce EE SE left A E EE EE 1 VREFDQ 121 Vss 61 A2 181 Al 2 Vss 122 DQ4 62 VDD 182 VDD 3 DQO 123 DQ5 63 NC CK1 183 VDD 4 DQ1 124 Vss 64 NC CK1 184 CK0 5 Vss 125 k 65 Von 185 TKO 6 DQS0 126 66 Von 186 VoD 7 DQS0 127 Vss 67 VREFCA 187 EVENT NC 8 Vss 128 DQ6 68 Par_In NC 188 A0 9 DQ2 129 DQ7 69 VDD 189 VDD 10 DQ3 130 Vss 70 A10 AP 190 BA1 11 Vss 131 DQ12 71 BA0 191 VDD 12 DQ8 132 DQ13 72 VDD 192 RAS 13 DQ9 133 Vss 73 WE 193 S0 14 Vss 134 EOS 74 CAS 194 VoD 15 DOSI 135 E 75 VoD 195 ODTO 16 DQS1 136 Vss 76 S1 NC 196 A13 17 Vss 137 DQ14 77 ODT1 NC 197 VDD 18 DQ10 138 DQ15 78 VDD
65. roup then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 40 Allowed time before ringback tDVAC for CK CK and DQS DQS DDR3 800 1066 1333 1600 tDVAC ps tDVAC ps tDVAC ps VIH Ldiff ac Slew Rate VIH Ldiff ac VIH Ldiff ac 270mV V ns 350mV 300mV DQS DQS only Optional min max min max min max gt 4 0 75 175 214 4 0 57 170 214 3 0 50 167 191 2 0 38 119 146 1 8 34 102 131 1 6 29 81 113 1 4 22 54 88 1 2 note 19 56 1 0 note note 11 lt 1 0 note note note note Rising input differential signal shall become equal to or greater than VIHdiff ac level and Falling input differential signal shall become equal to or less than VIL ac level Rev 1 0 Aug 2012 31 SK yi Single ended requirements for differential signals Each individual component of a differential signal CK DQS DQSL DQSU CK DQS DQSL of DQSU has also to comply with certain requirements for single ended signals CK and CK have to approximately reach VSEHmin VSELmax approximately equal to the ac level
66. s VIH ac VIL ac for ADD CMD signals in every half cycle DQS DQSL DQSU DQS DQSL have to reach VSEHmin VSELmax approximately the ac levels VIH ac VIL ac for DQ signals in every half cycle preceding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if VIH CA AC150 VIL CA AC150 is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK Or E VDO e erm Ee Se ERES ERES Ree RUE uS VSEHmina m9 mc K m e S Ber mk m RR T S K Es VDD 2 or NDDOI2 mna T EE CK or DQS VSELmax Single ended requirements for differential signals Note that while ADD CMD and DQ signal requirements are with respect to Vref the single ended compo nents of differential signals have a requirement with respect to VDD 2 this is nominally the same the transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Rev 1 0 Aug 2012 32 SK ni Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU DDR3 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max VSEH Single ended high level for strobes VDD 2 0 175 Note
67. s are MID LEVEL Table 6 IDD2NT and IDDQ2NT Measurement Loop Pattern e o z lt v8 2 BE pwll ES 18 s Q M gt GB x lt lt lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 O 0 0 0 0 0 0 0 0 0 2 D 1 1 1 1 0 0 0 0 0 F0 3 D 1 1 1 1 0 0 0 0 0 F l 0 2 5 1 4 7 repeat Sub Loop 0 but ODT 2 0 and BA 2 0 2 1 D 2 8 11 repeat Sub Loop 0 but ODT 1 and BA 2 0 2 8 L 3 12 15 repeat Sub Loop 0 but ODT 1 and BA 2 0 3 4 16 19 repeat Sub Loop 0 but ODT 0 and BA 2 0 4 5 20 23 repeat Sub Loop 0 but ODT 0 and BA 2 0 5 6 24 17 repeat Sub Loop 0 but ODT 1 and BA 2 0 6 7 28 31 repeat Sub Loop 0 but ODT 1 and BA 2 0 7 a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 0 Aug 2012 57 SK ni Table 7 IDD4R and IDDQ4R Measurement Loop Pattern v s z e SF amela v8 i 88 85 S 8 2s om C OS lt lt Z lt lt 0 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 2 3 DD 1 1 1 1 0 0 0 1 0 0 01 01 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 5 D 1 0 0 0 0 0 00 O 0 F 0 Pp 6 7 DD 11 11 1 1 0 0 0 0 0 F o E 1 8 15 repeat Sub Loop 0 but BA 2 0 1 8 L 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop
68. s associated with the command address and control bus Rev 1 0 Aug 2012 details of SPD and Thermal sensor please contact local SK hynix sales representative Vppspp gus Serial PD VDD D0 D17 Vir n D0 D17 VREFCA A D0 D17 VREFDQ D0 D17 Vss D0 D17 15 SK yi 8GB 1Gx72 2Rank of x8 page2 S0 mW L 1 2 S1 S 3 2 NC R BA N 0 4 E L AN 0 GE GE RAS s F WE RF CKE0 w L CKEL dd LL L ODIO dV e DDT WY am CK0 1209 EN 5 CKO CK1 1209 CK1 2 PAR IN wW OERR RESET RST RSOA CS0 SDRAMs D 3 0 D8 RSOB CS0 SDRAMs D 7 4 RSIA gt CSI SDRAMs D 12 9 D17 RS1B CSI SDRAMs D 16 13 RBA N 0 A BA N 0 SDRAMs D 3 S N 0 B BA N 0 SDRAMs D 7 A N 0 AINE SDRAMs D 3 0 A N 0 B A N 0 SDRAMs D 7 4 MN RAS SDRAMs D 3 0 D 12 RRASB RAS SDRAMs D 7 4 D 16 13 RCASA CAS SDRAMs D 3 0 D 12 8 D17 RCASB CAS SDRAMs D 7 4 D 16 13 RWEA gt WE SDRAMs D 3 0 D 12 8 D17 RWEB gt WE SDRAMs D 7 4 D 16 13 RCKEOA gt CKEO SDRAMs D 3 0 D8 RCKEOB CKE0 SDRAMs D 7 4 RCKE1A gt CKEI SDRAMs D 12 9 D17 RCKE1B gt CKEI SDRAMs D 16 13 RODTOA_ ODTO SDRAMs D 3 0 D8 RODTOB ODTO0 SDRAMs D 7 4 RODT1A ODTI SDRAMs D 12 9 D17 RODT1A gt ODTI SDRAMs D 16 13 PCKOA CK SDRAMs D 3 0 D8 PCKOB CK S
69. shoot Undershoot Specification for Clock Data Strobe and Mask DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 25 0 19 0 15 0 13 V ns Maximum undershoot area below VSS See Figure below 0 25 0 19 0 15 0 13 V ns CK CK DQ DOS DOS DM See figure below for each parameter definition Maximum Amplitude DD Volts S V sso Maximum Amplitude Time ns Overshoot Area Undershoot Area Clock Data Strobe and Mask Overshoot and Undershoot Definition Rev 1 0 Aug 2012 41 SK ni Refresh parameters by device density Refresh parameters by device density Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes PT command ro tRFC 90 110 160 260 350 ns REF command time Average periodic IREFI 0 C lt TcAsES85 C 7 8 7 8 7 8 7 8 7 8 us refresh interval 85 C lt Tease lt 95 0 3 9 3 9 3 9 3 9 3 9 us 1 Rev 1 0 Aug 2012 42 SK ni Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin DDR3 800 Speed Bins For specific Notes See Speed Bin Table Notes on page 47
70. sw B wesw 5 re Ly t e e RA YA Bs VS W Os NS pp En DOS S DOS 5 DOS S DOs S _ z DM z DM z N DQ 3 0 D7 DQ 3 0 D6 DQ 3 0 D47 EI D46 S g w BIE 5 wesw 5 95189 w 8 8 amp 91999 w 8 5 E E La La e La e DOs VS WY S s VSS WY Os VSS__ pa p md 7 p ES g GR E g W 0 3 0 D5 DQ 3 0 D4 3 DQ 3 0 D49 DQ 3 0 Dag Ei w 218 sw 8 we w 5 we 8 9999 8 5 e e e L RA A Bs VS WY Sds NES pa em i g BM S S a pas g M 00 3 0 D3 DQ 3 0 D2 DQ 3 0 D51 SERT D50 E 8 8 8 8 w 2188 8 we w 5 wile 8 218 sw 8 5 L all L La La Dus Tag ds Maia VSS_ pal SE q g Bu g eu S pos g W DQ 3 0 D1 3 DQ 3 0 DO 3 DQ 3 0 BES GEN D32 z 8 8 8 8 w 2184 5 882 we w 5 wile 8 io 218 8 5 d x x Ly e e Rev 1 0 Aug 2012 20 S de 32GB 4Gx72 Module 4Rank of x4 page2 vss DQS17 DQS17 vss CB 7 4 vss DQs12 DQs12 VSS DQ 31 28 vss DQS11 DQS11 VSS DQ 23 20 vss DQS10 DQS10 VSS DQ 11 8 VSS DQS9 DQS9 DQ 7 4 Vtt
71. sw s pos DQS DQ 3 0 D18 899 ws 8 5 A N O BALN O A N O BALN O Vtt 34 Rev 1 0 Aug 2012 lt g 2 HHE itii 9292 9 28 ig 10 2 2 1 d L L 1 I DQS8 A DOS Dos DQS8 w DQS Dos DQS vss DM DM 9 CB 3 0 AM DQ 3 0 D8 DQ 3 0 D26 8 i 2 8 ves 5 e BBB RIRE 5 DQs3 W DQS DOS3 W DOS vss DM DQI27 24 M9 DQ 3 0 D3 we 5 Dos s S H DQ 3 0 D21 H 9 8 io 28g 5 DQS2 A DOS DQS2 W DOS VSS DM DQ 19 16 24M DQ 3 0 D2 wk 8 5 DOS e 2 s DQ 3 0 D20 i 28g 5 DQS1 A DQS DQS1 W DQS VSS DM DO Blech DQ 3 0 D1 w Sig w 5 Dos DQS DQ 3 0 D19 A N O BA N O A N O BA N O w 2812 s w 5 DQS9 A DOS DQS9 W DOS VSS DM DQI 7 4 A DQ 3 0 D9 wesw 85 pos DQS DQ 3 0 D27 A N O BALN O A N O BALN O m in Vtt 34 17 SK ni 16GB 2Gx72 Module 2Rank of x4 page2 a o 9 2o m m m 95 TIT TEES elt z d PP g EE j MESS E
72. ternal clock Off CK and CK LOW CL see Table 1 BL 8 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Self Refresh Current Extended Temperature Range optional Tease 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Extended IDD6ET CKE Low External clock Off CK and CK LOW CL see Table 1 BL 83 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Rev 1 0 Aug 2012 53 SK yi Symbol Description Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD NRRD nFAW CL see Table 1 BL 88 f AL CL 1 CS High between ACT and RDA Command Address Bank Address Inputs partially toggling according to Table Ipp7_ 10 Data IO read data burst with different data between one burst and the next one according to Table 10 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different address ing wee Table 10 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 10 a Burst Length BL8 fixed by MRS set M
73. u B w Elsi w 5 95189 w 8 8 amp 91999 8 5 E E Ly e La DOs VSS jal Dos VSS AW Das VSS pa SC 7 S 5 z 2 W DQ 3 0 D33 DQ 3 0 D32 A DQ 3 0 D57 DQ 3 0 Do6 z w 218 sw 8 wiki sw 8 wikis 8 9999 8 5 Ly Ly 1 1 RA VSS jal RA VSS LW Das VSS pa SC E W DQ 3 0 D35 S DQ 3 0 D34 DQ 3 0 D55 ERG D54 E w 2188 4 8 wle 8 we 8 218 8 5 x x e Ly Le L e V SPD DDSPD X VDDSPD VDDSPD SAO SAO VDD DO D71 x EE EVENT EVENT SPD with SA1 SA1 Vrr Integrated EEGA l T SCL SCL SA2 SA2 VREFDQ D0 D71 SDA SDA VSS VSS Vss DO D71 Plan to use SPD with Integrated TS of Class B and 23 SK yi 32GB 4Gx72 Module 4Rank of x4 page5 SU L ARSOA gt CS1 SDRAMs D1 D3 D5 D7 D9 BI J I BRS2A gt CS1 SDRAMs D45 D47 D49 D51 D53 1 2 D19 D21 D23 D25 D27 1 2 D63 D65 D67 D69 D71 ARSOB CS1 SDRAMs D11 D13 D15 D17 BRS2B CS1 SDRAMs D37 D39 D41 D43 R D29 D31 D33 D35 R D55 D57 D59 D61 SI E L ARS1A CS0 SDRAMs DO D2 D4 D6 D8 3 E I BRS3A CS0 SDRAMs D44 D46 D48 D50 D52 G DI8 D20 D22 D24 D26 G D62 D64 D66 D68 D70 ARS1B CS0 SDRAMs D10 D12 D14 D16 BRS3B CS0 SDRAMs D36 D38 D
74. use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Aug 2012 56 gt gt SK hynix Table 5 IDD2N and I DD3N Measurement Loop Pattern Z S o z Si 6 s s Bg i g Pe Bee RS 3 ES 8 8 one Q M gt GB x lt lt lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 B 1 1 1 1 0 0 01 01 1 0 00 F O 3 D 1 1 11 1 01 01 01 10 10 0Fl ER 2 5 1 4 7 repeat Sub Loop 0 use BA 2 0 1 instead D 2 8 11 repeat Sub Loop 0 use BA 2 0 2 instead E 3 12 15 repeat Sub Loop 0 use BA 2 0 3 instead 4 16 19 repeat Sub Loop 0 use BA 2 0 4 instead 5 20 23 repeat Sub Loop 0 use BA 2 0 5 instead 6 24 17 repeat Sub Loop 0 use BA 2 0 6 instead 7 28 31 repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signal
75. ximum DC Ratings Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss 0 4 V 1 80 V V 13 VDDQ oltage on VDDQ pin relative to Vss 0 4 V 1 80 V V 1 3 Vin Vout Voltage on any pin relative to Vss 0 4 V 1 80 V V 1 Tstg Storage Temperature 55 to 100 at 1 2 Notes 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for extended periods may affect reliability Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to J ESD51 2 standard VDD and VDDQ must be within 300mV of each other at all times and VREF must not be greater than 0 6XVDDQ When VDD and VDDQ are less than 500mV VREF may be equal to or less than 300mvV DRAM Component Operating Temperature Range Temperature Range Symbol Parameter Rating Units Notes T Normal Operating Temperature Range 0 to 85 C 1 2 OPER Extended Temperature Range 85 to 95 C 1 3 Notes 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For mea sure

Hynix 16GB DDR3 PC3-12800

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