Super Talent Technology 4GB DDR3 PC3-10600 1333MHz
Contents
1. http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 4 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 8 0 Functional Block Diagram 4GB 512Mx64 Module Populated as 2 ranks of x8 Yj td T x DISA age pasts 5 4a DQS1 Ww DMI sf 3333 ie Dao D1 oan rete cate Ooms ets oot Dost x DSS CM _ BRRRERRE 3 Rank 0 U1 UB BARI 84 20 DDR SDRAM Rank t U10 U17 Ananas AII413 DDR3 SDRAM us RASe RAS DDR3 SDRAM scL SPD EEPROM Da on tank CASs CASe DDR3 SDRAM WP AD AI A NES WEp DDA3 SDRAM cri tack CKE CKEO Rank 0 VaSAD SAY saz aa mi CKE gt CKE Rank I ODTO oODTc Rark Voosep SPD EEPROM ODT ODTT Rank 1 RESETS RESET DOR3 SDRAM Von DDR3 SDRAM V Address command control and dock line terminations bal DERISRAM CEO CKET ADII33 Vreca DORI SDRAM OAA ane v DRI SDRAM ODTO ODTI BAY SDRAM m a1 0 Ves DDR3 SDRAM cro Oct DDR3 crag Oct SDRAM Hoo The ZQ ball on each DDR3 component is connected to an external 2400 1 resistor that is tied to ground Used for the calibration of the component s on die termination and output driver http www supertalent com oem Products and Specifications discussed herei2. Write leveling output delay tWLO Write leveling output error tWLOE http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 9 2006 Super Talent Tech Corporation SUPER x TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 11 0Physical Dimensions 256Mbx8 Based 512Mx64 2 rank FRONT VIEW 133 5005 24 13220911240 22 50 11 20 20 85 1 175 2 50 0 058 D 1 2 200 991 TY j 17 pos 1 7 pos 2 20 0 087 TYP 8 5 10 374 1 45 0 087 TYP TF 54 08 2 15 PIN 120 we 1230 486 Tr BACK VIEW HHEG EGE L JEN C22 p1w 24 Tye ia 3 06 0 12 TY _ pin 2ao ia 121 sa pisi re 710 2 79 _ 47 0 1 88 TYP Tw Tolerances 0 005 13 unless otherwise specified http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 10 2006 Super Talent Tech Corporation
3. ps DQ high impedance time from CK CK tHZ DQ ps Data setup time to DQS DQS referenced to Vih ac Vil ac levels tDS base ps Data hold time to DQS DQS referenced to Vih ac Vil ac levels tDH base ps DQ and DM Input pulse width for each input tDIPW ps Data Strobe Timing DQS DQS READ Preamble tRPRE 0 9 tCK DQS DQS differential READ Postamble tRPST 0 3 tCK DQS DQS output high time tQSH 0 4 tCK avg DQS DQS output low time tQSL 0 4 tCK avg DQS DQS WRITE Preamble tWPRE 0 9 tCK DQS DQS WRITE Postamble tWPST 0 3 tCK DQS DQS rising edge output access time from rising CK CK tDQSCK 255 ps DQS DQS low impedance time Referenced from RL 1 tLZ DQS 500 ps DQS DQS high impedance time Referenced from RL BL 2 tHZ DQS 250 ps DQS DQS differential input low pulse width tDQSL 0 45 tCK DQS DQS differential input high pulse width tDQSH 0 45 tCK DQS DQS rising edge to CK CK rising edge tDQSS 0 25 tCK avg DQS DQS faling edge setup time to CK CK rising edge tDSS 0 2 tCK avg DQS DQS faling edge hold time to CK CK rising edge tDSH 0 2 tCK avg DLL locking time tDLLK 512 nCK internal READ Command to PRECHARGE Command delay tRTP max 4tCK 7 5ns Delay from start of
4. tWR tCk Timing of WRA command to Power Down entry BL8OTF BL8MRS BL4OTF tWRAPDEN WL 4 WR 1 WL 2 tWR tCK avg Timing of WR command to Power Down entry BL4MRS tWRPDEN http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 8 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 11 4 AC Timing Parameters amp Specifications con t DDR3 1333 min max tWRAPDEN WL 2 WR 1 Parameter Symbol Timing of WRA command to Power Down entry BL4MRS Timing of REF command to Power Down entry tREFPDEN 1 Timing of MRS command to Power Down entry tMRSPDEN tMOD min ODT Timing ODT high time without write command or with wirte commandand BC4 ODTH4 ODT high time with Write command and BL8 amp ODTH8 Asynchronous RTT tum on delay Power Down with DLL frozen tAONPD ns Asynchronous RTT tum off delay Power Down with DLL frozen tAOFPD ns ODT turn on tAON ps RTT_NOM and RTT_WR turn off time from ODTL off reference tAOF 5 4 tCK avg RTT dynamic change skew tADC 3 tCK avg Write Leveling Timing First DQS pulse rising edge after tDQSS margining mode is programmed tWLMRD DQS DQS delay after tDQS margining mode is programmed tWLDQSEN Setup time for tDQSS latch tWLS Hold time of tDQSS latch tWLH
5. DQSO_P Vss 47 Vss 167 NC TEST DQ39 Vss DQ6 48 NC 168 RESET_N Vss DQ2 DQ7 KEY s DQ44 DQ3 Vss 49 NC 169 CKE1 DQ45 Vss DQ12 50 CKEO 170 Vss DQ8 DQ13 51 VDD 171 A15 s DM5 DQS14_P DQ9 Vss 52 BA2 172 DQS14_N Vss DMI1 DQS10_P 53 NC Err Out 173 Vss DQSI_N DQSIO_N 54 VDD 174 A12 DQ46 DQS2_P Vss 55 All 175 A9 DQ47 Vss DQ14 56 A7 176 Vss DQ10 DQI5 57 VDD 177 A8 s DQ52 DQI1 Vss 58 A5 178 A6 DQ53 Vss DQ20 59 A4 179 Vss DQ16 DQ21 60 VDD 180 A3 DM6_DQS15_P DQ17 Vss 61 A2 181 Al DQSI5_N Vss DQS11_P 62 VDD 182 VDD Vss DQS2_N DQS1I1_N 63 CKI_P NC 183 VDD s DQ54 DQS2_P Vss 64 CKI_N NC 184 CK0_P DQ55 Vss DQ22 65 VDD 185 CKO_N Vss DQ18 DQ23 66 VDD 186 VDD DQ60 DQ19 Vss 67 VrerCA 187 NC EVENT DQ61 Vss DQ28 68 NC Par_In 188 AO Vss DQ24 DQ29 69 VDD 189 VDD S DM7 DQS16_P DQ25 Vss 70 A10 AP 190 BAI DQS1I6_N Vss DM3 DQS12_P 71 BAO 191 VDD Vss DQ3_N 153 DQS12_N 72 VDD 192 RAS_N s DQ62 DQ3_P Vss 73 WE 193 SO_N DQ63 Vss 155 DQ30 74 CAS 194 VDD Vss DQ26 156 DQ31 75 VDD 195 ODTO VppSPD DQ27 157 Vss 76 S1 196 A13 SA1 Vss 158 NC 77 ODT1 197 VDD NC NC 78 VDD 198 NC Vss NC 160 Vss 79 2 NC 199 Vss Vor 80 Vss 200 NC No Connect RFU Reserved for Future Use 1 Par_in and Err_out pins are intended for register control functions O oo NoU FWY ee o http www supertalent com oem Products and Specifications discussed herein are subject to change
6. internal write transaction to internal read command tWTR max 4tCK 7 5ns WRITE recovery time tWR 15 Mode Register Set command cycle time tMRD 4 Mode Register Set command update delay tMOD max 12tCK 15ns CAS to CAS command delay tCCD 4 z Auto precharge write recovery precharge time tDAL min WR roundup tRP tCK AVG Products and Specifications discussed herein are subject to change without notice 7 2006 Super Talent Tech Corporation http www supertalent com oem SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 11 3 AC Timing Parameters amp Specifications con t DDR3 1333 Parameter Symbol m n max Multi Purpose Register Recovery Time tMPRR 1 ACTIVE to PRECHARGE command period tRAS 36 70 000 max ACTIVE to ACTIVE command period for 1KB page size tRRD 4tCK 6ns max 4tCK 7 5ns Four activate window for 1KB page size tFAW 30 ACTIVE to ACTIVE command period for 2KB page size tRRD Four activate window for 2KB page size tFAW 45 Command and Address setup time to CK CK referenced to Vih ac Vil ac levels tlS base 65 Command and Address hold time from CK CK referenced to Vih ac Vil ac levels tlIH base 140 tIS base AC150 Control amp Address Input pulse width for each input tIPW 620 Command and Address setup time to CK CK refe
7. without notice 3 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 6 0 DIMM Pin Description Pin Name Function Pin Name Function AO A15 Address input Multiplexed ODT0 ODT1 On Die Termination A10 AP Address Input Auto pre charge CB0 CB7 ECC Data check bits Input Output BAO BA2 Bank Select DQ0 DQ63 Data Input Output CKO CK2 CKO CK2 Clock input DQSO DQS8 Data strobes negative line CKEO CKE1 Clock enable input DM 0 8 Data Masks Data strobes Read S0 S1 Chip select input DQS0 DQS8 Data Strobes RAS Row address strobe RFU Reserved for future used CAS Column address strobe SDRAM I O termination power supply WE Write Enable Memory bus test tool SCL SPD Clock Input Core Power SDA SPD Data Input Output T O Power SA0 SA2 SPD Address Ground Par_In Parity bit for address amp Control bus SDRAM Input Output Reference Supply Err_Out Parity error found in the Address and Control bus Serial EEPROM Power Supply RESET Register and PLL control pin Command Address Reference Supply 7 0 Address Configuration Row Address A0 A14 Bank Address BAO BA2 Column Address A0 A9 Organization 256Mx8 2Gb base Auto Pre charge A10 AP
8. SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM DDR3 Unbuffered DIMM Module 4GB based on 2Gbit component TFBGA with Pb Free RoHS 2002 95 EC Revision 1 0 MAY 2007 Initial Release http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY DDR3 SDRAM 240 Pin Unbuffered DIMM 1 0 Feature JEDEC standard 1 5V 0 075V Power Supply VDDQ 1 5V 0 075V Programmable CAS latencies 6 7 8 9 10 11 13 Programmable Additive Latency Posted CAS 0 CL 2 or CL 1 clock Programmable CAS Write Latency CWL 5 DDR3 800 6 DDR3 1066 7 DDR3 1333 8 DDR3 1600 and 9 DDR3 1866 400MHz fCK for 800Mb sec pin 533MHz fCK for 1066Mb sec pin 667MHz fCK for 1333Mb sec pin 8300MHz fCK for 1600Mb sec pin 900MHz fCK for 1866Mb sec pin Bi directional Differential Data Strobe Burst Length 8 Interleave without any limit sequential with starting address O00 only 4 with tCCD 4 which does not allow seamless read or write either On the fly using A12 or MRS On Die termination using ODT pin 8 independent internal bank Asynchronous Reset Average Refresh Period 7 8us at lower than a TCASE 85 C 3 9us at 85 C lt TCASE lt 95 C Serial presence detect with EEPROM DIMM Dimension Nominal 30 00 mm high 133 35 mm wide Based on JEDEC standard
9. ck Cumulative error across 2 cycles tERR 2per Cumulative error across 3 cycles tERR 8per Cumulative error across 4 cycles tERR 4per Cumulative error across 5 cycles tERR 5per Cumulative error across 6 cycles tERR 6per Cumulative error across 7 cycles tERR 7per Cumulative error across 8 cycles tERR 8per Cumulative error across 9 cycles tERR 9per Cumulative error across 10 cycles tERR 10per http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 6 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 11 2 AC Timing Parameters amp Specifications con t Parameter Symbol DDR3 1333 min max Cumulative error across 11 cycles tERR 11per 210 210 ps Cumulative error across 12 cycles tERR 12per 215 215 ps Cumulative error across n 13 14 49 50 cycles tERR nper tERR nper min 1 0 68ln n tJIT per min tERR nper max 1 0 68In n tUIT per max ps Absolute clock HIGH pulse width tCH abs 0 43 tCK avg Absolute clock Low pulse width tCL abs 0 43 tCK avg Data Timing DQS DQS to DQ skew per group per access tDQSQ ps DQ output hold time from DQS DQS tQH tCK avg DQ low impedance time from CK CK tLZ DQ
10. n are subject to change without notice 5 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 9 0 AC amp DC Operating Conditions Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Symbol Parameter Min Vpop Supply Voltage 1 425 VDDQ Supply Voltage for Output 1 425 VrerDQoc T O Reference Voltage DQ 0 49 VDpo VrerCA po T O Reference Voltage CMD Add 0 49 Vppo Ver Termination Voltage 0 49 Vppo 10 0 Capacitance Max Symbol Parameter Condition CCK Input capacitance CK and CK CII Input capacitance CKE and cs CI2 Input capacitance Addr RAS CAS WE CIO Input capacitance DQ DM DQS DOS 11 1 AC Timing Parameters amp Specifications AC operating conditions unless otherwise noted Parameter Symbol DDR3 1333 Minimum Clock Cycle Time DLL off mode tCK DLL_OFF ns Average Clock Period tCK avg ps tCK avg min tJIT tCK avg max tJIT per min per max Average high pulse width tCH avg 0 47 0 53 tCK avg Clock Period tCK abs ps Average low pulse width tCL avg 0 47 0 53 tCK avg Clock Period Jitter tUIT per 80 80 ps Clock Period Jitter during DLL locking period tJIT per Ick 80 80 ps Cycle to Cycle Period Jitter tulT cc Cycle to Cycle Period Jitter during DLL locking period tulT cc I
11. reference Raw Cards Lay out RoHS compliant Gold plated contacts 2 0 Ordering Information Part number Density Module Component Organization composition Component PKG Description W1333UB4GV 4GB 512Mx64 256Mx8 16 TFBGA 4GB 2Rx8 PC3 10600U 3 0 Key Timing Parameters DDR3 1333 CL tRCD tRP 9 9 9 CAS Latency 9 tCK min 1 5 tRCD min 13 5 tRP min 13 5 tRAS min 36 tRC min 49 5 4 0 Absolute Maximum DC Rating Symbol Parameter Rating 0 4 1 975 0 4 1 975 0 4 1 975 0 4 1 975 55 100 Vin Vout Voltage on any pin relative to Vss Vpop Voltage on Vpp amp Vppg supply relative to Vss Vppe Short circuit current VoppL Power dissipation TstG Storage Temperature Products and Specifications discussed herein are subject to change without notice 2 2006 Super Talent Tech Corporation http www supertalent com oem SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 5 0 DIMM Pin Configurations Front side Back side Pin Front Pin Back Pin Front Pin Back i i Back VrerDQ 121 Vss 41 Vss 161 DM8 DQS17_P DQ37 Vss 122 DQ4 42 NC 162 DQSI7_N Vss DQO DQ5 43 NC 163 Vss s DM4 DQS13_P DQ1 124 Vss 44 Vss 164 NC DQS13_N Vss DM0 DQS9_P 45 NC 165 NC Vss DQSO_N NC DQS9_N 46 NC 166 Vss S DQ38
12. renced to Vih ac Vil ac levels 654125 Calibration Timing Power up and RESET calibration time tZQinitl Normal operation Full calibration time tZQoper Normal operation short calibration time tZQCS 64 Reset Timing max 5tCK tRFC Exit Reset from CKE HIGH to a valid command 10ns Self Refresh Timing max 5tCK tRFC 10ns Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK min tCKE min 1tCK max 5tCk 10ns max 5tCkK 10ns Exit Self Refresh to commands not requiring a locked DLL tXS Minimum CKE low width for Self refresh entry to exit timing tCKESR Valid Clock Requirement after Self Refresh Entry SRE tCKSRE Valid Clock Requirement before Self Refresh Exit SRX tCKSRX Power Down Timing Exit Power Down with DLL on to any valid command Exit Precharge Power Down with XP max DLL frozen to commands not requiring a locked DLL 3tCK 6ns Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL tXPDLL max 10tCK 24ns CKE minimum pulse width tCKE max 3tCK 5 625ns Command pass disable delay tCPDED 1 Power Down Entry to Exit Timing tPD tCKE min 9 tREFI iming of ACT command to Power Down entry tACTPDEN 1 Timing of PRE command to Power Down entry tPRPDEN 1 Timing of RD RDA command to Power Down entry tRDPDEN RL 4 1 Timing of WR command to Power Down entry BL8OTF BL8MRS BL4OTF tWRPDEN WL 4
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