Epson RX-8564LC Clock User Manual
Contents
1. The shaded part indicates where a GND pattern should be set without getting too 170 C 220 C close to a signal line 1 5 C s 100s 35s Pre heating area Stable Melting area time s Page 9 ETM12E 01 RX 8564 LC EPSON TOVI M 12 Overview of Functions and Description of Registers 12 1 Overview of Functions 1 Clock functions This function is used to set and read out month dav hour date minute second and vear last two digits data Any two digit year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099 x For details see 13 1 Description of Registers 2 Fixed cycle interrupt generation function The fixed cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set between 244 14 us and 255 minutes When an interrupt event is generated the INT pin goes to low level L and 1 is set to the TF bit to report that an event has occurred Two types of operations can be selected for this function level interrupt mode and repeated interrupt mode x For details see 13 2 Fixed cycle Interrupt Function 3 Alarm interrupt function The alarm interrupt generation function generates interrupt events for alarm settings such as date day hour and minute settings When an interrupt event occurs the AF bit value is set to 1 and the INT pin goes to low level to indicat2. RX 8564 LC 1 NC 12 NC 2 NC 11 CLKOE 3 N C 10 VDD 4 NC 9 CLKOUT 5 INT 8 SCL 6 GND 7 SDA VSOJ 12pin 3 2 Pin Functions Signal Game O Function Input This is the serial clock input pin for IC Bus communications This pin s signal is used for input and output of address data and ACK bits BEE synchronized with the serial clock used for DC communications Bi Directional e Since the SDA pin is an N ch open drain pin during output be sure to connect a suitable pull up resistance relative to the signal line capacitv The CLKOUT pin is a clock output pin C MOS output with the output control function The CLKOE pin can be used in combination with the FE bit FD1 bit and FDO bit to control the output mode of the CLKOUT output pin CLKOUT Output The CLKOE input pin can be used in combination with the FE bit FD1 bit and FDO bit to select the frequency output from the CLKOUT output pin 32 768 kHz 1024 Hz 32 Hz or 1 Hz or to stop output When output is stopped the CLKOUT output pin is at low level L CLKOE pin FE CLKOUT pin ur Li Output LEMOS H CLKOE OFF SC mw 1 OFF L KEE GE During the initial power on when power is applied from 0 V if the CLKOE input pin is at high level H the power on reset function selects 32 768 kHz as the frequency This pin outputs alarm signals fixed timer interrupt signals and other interrupt signals at low level L
3. 1 If 32 768 kHz has been selected as the output frequency output will continue at 32 768 kHz 2 If any other output frequency was selected 1024 Hz 32 Hz or 1 Hz CLKOUT output is stopped 3 When the STOP bit 1 the IC BUS bus timeout function is disabled Note this with caution When the STOP bit 0 these operations are resumed stop mode is canceled 0 5 seconds after the STOP bit value is changed from 1 to 0 the second value is updated without waiting for a full second to elapse This operation occurs once only after changing the STOP bit value This is done to keep the error margin to within 40 5 seconds in relation to the actual time whenever the clock value is changed via any timing Page 12 ETM12E 01 RX 8564 LC EPSON TOY M 13 1 2 Control register 2 Reg 01 h Address h Function bit7 bit6 bit5 i bit4 bits bit2 bit bito Control 2 0 x 0 TTP AF TF AE TIE This register is used to monitor various interrupt event settings and the conditions under which various interrupt related events occur 1 TI TP bit Interrupt Signal Output Mode Select Interrupt Periodic When a fixed cycle timer interrupt event occurs when the TF bit goes from O to 1 this bit specifies whether the interrupt operation occurs just once or repeatedly Writing 1 to this bit sets repeated operation Writing O to this bit sets single shot operation
4. O RTC s internal operation Write operation x Before starting the fixed cycle timer interrupt function each time be sure to write a value preset value Reg OF h as the timer s down counter value when TE 0 Note Note with caution that the preset value must be set or reset to enable correct operation Before entering operation settings we recommend first clearing the TE bit to 0 and then clearing the TF and TIE bits to O in that order so that all control related bits are zero cleared set to operation stop mode to prevent hardware interrupts from occurring inadvertently while entering settings 1 When the TE bit value is changed from O to 1 the fixed cycle timer s countdown begins 2 A fixed cycle timer interrupt event starts a countdown based on the countdown period source clock When the count value changes from 01h to 00h an interrupt event occurs After the interrupt event that occurs when the count value changes from O1hto OOh the counter automatically reloads the preset value and again starts to count down Repeated operation 3 When a fixed cycle timer interrupt event occurs 1 is written to the TF bit 4 When the TF bit 2 1 its value is retained until it is cleared to zero 11 Even when the TE bit is cleared to zero the TF bit value is retained as 1 and the TIRQ pin status is not reset 5 If the TIE bit 1 when a fixed cycle timer
5. 1 its value is retained until it is cleared to zero Even when the TE bit is cleared to zero the TF bit value is retained as 1 and the INT pin status is not reset 7 After the TF bit is cleared to zero the TIRQ pin is set to Hi Z status regardless of the TIE bit s value Page 23 ETM12E 01 RX 8564 LC EPSON TOY M 13 2 4 2 Operation example of repeated interrupt mode TI TP 1 e After an interrupt event has occurred execution of the operation is automatically repeated continuously Fixed cycle timer operation Fixed cycle timer operation starts stops 1 1 TE bit Fixed cycle timer operation in progress AG TT E H m 4 Tod 4 TIE bit o Hi z INT output Lr EIN i f M DRE Low level is held during f Z A SE gi 3 de tRTN even if the TF bitis 11 1 it A cleared to zero TF bit value is held as 1 1 KI i even if the TE bit is cleared to 1st period Sie 2nd period RE 3rd period i zero Event In oth soon H 2m Pi mg occurs t Ti is As long as the TE bit value i i o 1 is O the countdown is The fixed cycle timer function countdown starts when the TE bit value is changed from 0 to 1 MNT Stopped and no events occur Before starting the fixed cycle timer interrupt function each time be sure to write a value preset i value Reg OF h as the timers down counter value when TE
6. Description of Registers 10 12 1 Overview of Functions smenenmennnnznnznznznneznnnnenznznznninn nn entente aa nnns 10 12 2 Baglster table oec Det tt ADR A ERN CAII dou up SLE CUIU to 11 13 Description of FURCHlols ite haee eh end RS 12 13 1 Description of FO ISTONS EE 12 13 1 1 Control register 1 Reg 00 h Lara 12 13 1 2 Control register 2 Reg 01 Il 13 13 1 3 Clock counter Reg 02 h to 04 Ill 14 13 1 4 Calendar counter Reg 05 h 07 h 08 hl nee enen nanna 15 19 1 5 Day counter Reg 6 h a tret ket Rn tex tton a eA 15 13 1 6 Alarm registers Reg 09 h to oC 16 13 1 7 Timer setting register Reg OE hl 16 13 1 8 Down counter for fixed cycle timer Reg OF h 16 13 1 9 CLKOUT output register Reg OD h Learn nr 17 13 2 Fixed cycle Timer Interrupt Function EEN 18 13 3 Alarm Interrupt Function essent 25 13 4 INT L Interrupt Output When Interrupt Function Operates 28 19 5 m ON rn Le tei teet al ete aede eed 29 13 6 Reading Writing Data via the 12C Bus Intertace 32 RX 8564 LC EPSON TOYOCOM Low power consumption Small size thin model package I C Bus Interface Real Time Clock Module RX 8564 LC e Built in frequency adjusted 32 768 kHz crystal unit e Interface type 400 kHz two wire I C bus interface e Wide operating voltage range 1 8V to 5 5V e Wide timekeeper voltage ra
7. The INT interrupt output pin is shared as the output pin for two kinds of interrupt events events related to the fixed cycle timer interrupt function and events related to the alarm interrupt function When an interrupt occurs when INT is at low level L read the TF and AF flags to determine which type of interrupt event occurred which flag value changed to 1 2 How to prevent INT pin from going to low level L To prevent the INT pin from going to low level L clear all TIE and AIE bits to zero To detect when an interrupt event has occurred without having to set the INT pin to low level monitor the TF and AF flag bit values to see if the target interrupt event has occurred i e to see if either flag bit value changes from 0 to 1 Page 28 ETM12E 01 RX 8564 LC EPSON TOY M 13 5 Flow Charts e The flow charts shown below are intended as examples oniv x These examples are written to be easilv understood and therefore thev mav not be as efficient as the actual processing Ways to boost processing efficiency include setting several processes as parallel processes and changing the sequence of operations in areas where it does not create any problems Some of the processing described here may not be necessary under certain use conditions x To ensure that operations are as expected make adjustments according to the use conditions use environment 1 Initialization example Initialization
8. This pin is an open drain pin HEISE This pin connects to the plus side of the power 9 This pin connects to the minus side ground of the power owe pom This pin is not connected internally Be sure to connect using OPEN or GND or VDD Note Be sure to connect a bypass capacitor rated at least 0 1 uF between VDD and GND KUN Ta RX 8564 LC EPSON TOV M 4 External Dimensions Marking Layout 4 1 External Dimensions RX 8564 LC VSOJ 12pin e External dimensions e Recommended soldering pattern 25 f os a 3 UU Ub eo y al S e 0 5 627 Y st br 3 UU eo 1 oe Faas a 0 08 M 2 77 ana Je le 1 140 Unit mm 4 2 Marking Layout RX 8564 LC VSOJ 12pin E 8564 Q A123B 1 Pin Mark Production lot x Contents displayed indicate the general markings and display but are not the standards for the fonts sizes and positioning Page 3 ETM12E 01 RX 8564 LC EPSON TOYO M 5 Absolute Maximum Ratings GND 0 V Supply Voltage IA Between VDD and GND 0 5 to 46 5 MA Input Voltage WES Input pin GND 0 5 to VDD 0 5 Output Voltage IA JINT pin GND 0 5 to VDD 0 5 Storage Stored bare product after 5 6 Recommended operating conditions GND 0 V I C BUS access Operating supply voltage at 400 kHz 1 8 to 5 5 RU 1 See 8 1 DC Electrical Charac
9. first second update occurs 500 ms later To next process 5 Example of clock and calendar read processing Read current time Read current time e The required information among the Year Month Day day of week hour minute second data is read within one second x There is no need to manipulate the STOP bit Page 30 ETM12E 01 RX 8564 LC EPSON TOY M 6 Example of timer interrupt function setting i Cancel timer interrupt function ii Set timer interrupt function Start timer interrupt function i Set timer interrupt function TE lt 0 TF 0 TIE 0 Set TI TP bit Set TIE bit Set TD1 TDO bit Initialize counter TEc 1 To next process e Zero clear the TE bit to stop the timer interrupt function e Zero clear the TF bit and TIE bit to cancel the previous timer interrupt output IRQ output 1 e Select the operation mode one shot interrupt or repeated continuous interrupts 1 When repeated continuous interrupts are selected Write 1 to the TI TP bits 2 When one shot interrupt is selected Write 0 to the TI TP bits 2 e Select event triggered INT output output do not output interrupt when at low level 1 Output interrupt when at low level Write 1 to the TIE bit 2 Do not output interrupt when at low level Write 0 to the TIE bit e Set the timer s countdown period 2 sour
10. interrupt occurs INT pin output goes low 9 If the TIE bit 0 when a fixed cycle timer interrupt occurs INT pin output remains Hi Z 6 Output from the INT pin remains low during the tRTN period following each event after which it is automatically cleared to Hi Z status 7 When the next interrupt event occurs the INT is again set to low level L 4 In this operation example the TF bit is not cleared to zero so the 1 value is held 8 When INT is at low level L it remains at low level during the tRTN period even if the TF bit value is changed from 1 to 0 10 Changing the TE bit value from 1 to O stops the fixed cycle timer s function stops the countdown Page 24 ETM12E 01 RX 8564 LC EPSON TOY M 13 3 Alarm Interrupt Function The alarm interrupt generation function generates interrupt events for alarm settings such as date dav hour and minute settings When an interrupt event occurs the AF bit value is set to 1 and the INT pin goes to low level to indicate that an event has occurred When an alarm interrupt event occurs low level output from AIRQ is not automatically reset it can be reset only intentionally and the low level status of AIRQ is retained Example of INT Rs operation AlE 2 1 AF 0 71 AF 2 1 5 O or AIE 1 gt 0 13 3 1 Diagram of alarm interrupt function AIE bit Ce idi Hi z INT output ih
11. jq AF bit ka H SX i Event jm f m occurs SE RTC internal operation 01 98 Write operation 1 The minute hour day of week weekday and date at which an alarm interrupt event will occur is set in advance and the interrupt event occurs when the current time matches this pre set time 2 When a time alarm interrupt event occurs the AF bit values becomes 1 3 When the AF bit 1 its value is retained until it is cleared to zero 4 If AIE 1 when an alarm interrupt occurs the INT pin output goes low When an alarm interrupt event occurs INT pin output goes low and this status is then held until it is cleared via the AF bit or AIE bit 5 If the AIE value is changed from 1 to 0 while INT is low the INT status immediately changes from low to Hi Z x After the alarm interrupt occurs and before the AF bit value is cleared to zero the INT status can be controlled via the AIE bit 6 If the AF bit value is changed from 1 to O while INT is low the INT status immediately changes from low to Hi z 7 If the AIE bit value is 0 when an alarm interrupt occurs the INT pin status remains Hi z Page 25 ETM12E 01 RX 8564 LC EPSON TOY M 13 3 2 Alarm interrupt function registers Address H Function bit7 bit6 bits bit4 bits bit2 bit bito 0 a Panes Pare Pe Peet ae META Before entering settings for operations we recommend Fee a 0 to the AI
12. mode TI TP bit 1 After an interrupt event occurs the operation is automatically repeated When an interrupt event occurs during repeated interrupt mode INT output goes to low level only during the tRTN period and then it is automatically canceled and returns to Hi Z status However even after returning to Hi Z status similar INT output is obtained after the next interrupt event occurs Afterward this is repeated until fixed cycle timer operation is stopped xExample of INT operation Auto reset tim period TIE 1 TIES 1 5 0 TF 0 TF 0 gt 4 TE 0 gt 1 Page 18 ETM12E 01 RX 8564 LC EPSON TOY M 3 Overview of fixed cvcle timer interrupt function 1 Changing the TE Timer Enable bit value from 0 to 1 starts operation of the fixed cycle timer interrupt function x Before starting the fixed cycle timer interrupt function each time be sure to write a value preset value Reg OF h as the down counter value for the timer when TE 0 Note Note with caution that the preset value must be set or reset to enable correct operation 2 When the TE bit 1 the timer s down counter Timer Register Reg OF h counts down once per cycle countdown cycle of the source clock that was selected via the TD1 and TDO bits Timer countdown interval select bits 1 and 0 Timer cycle Period Source clock x value preset value set to timers
13. mode to prevent hardware interrupts from occurring inadvertently while entering settings 1 TI TP bit Interrupt Signal Output Mode Select Interrupt Periodic When a fixed cycle timer interrupt event occurs this bit selects whether to end the operation after one iteration or to repeat the operation TI TP Data Description Level interrupt mode 0 Fixed cycle timer interrupt function operates one time only Write Read Another operation can be set via various bit settings Repeated interrupt mode Fixed cycle timer interrupt function operates repeatedly 2 TD1 TDO bits Timer countDown interval select 1 0 These bits specify the fixed cycle timer interrupt function s countdown period source clock Four different periods can be selected via combinations of these two bit values INT auto recovery time tRTN TD1 TDO luring repeated interrupt mode Ae bit 1 bit 0 Source clock TERT atu Presi Elie n 1 1 n o o 4096 H 244 14 us cycle 122 us 244 us WR 0 1 64Hz 15 625 ms cycle 7 813ms 15 625 ms 1 0 1Hz Updated per second 15 625 ms 15 625 ms 1 1 1 60Hz Updated per minute 15 625 ms 15 625 ms x1 During repeated interrupt mode TI TP bit 1 the auto recovery time tRTN when the INT pin is switched from low level to Hi Z varies according to the source clock and preset value as shown above 2 The countdown when a 1 Hz s
14. the following equations 0 Afr a 0T 0x 2 AfT Frequency deviation in any temperature a 1 C Coefficient of secondary temperature 0 035 0 005 x 1078 C e gr C Ultimate temperature 25 5 C ox C Any temperature a Ei e o Frequency Aft To determine overall clock accuracy add the 0 50 frequency precision and voltage characteristics Temperature C AU Af fo ATT Afv e Af f Clock accuracv stable frequencv in anv temperature and voltage Af fo Frequency precision e AfT Frequency deviation in any temperature Afv Frequency deviation in any voltage Howto find the date difference Date Difference Af f x 86400 Sec For example Af f 11 574 x 10 is an error of approximately 1 second day 2 Current and voltage consumption characteristics 2 1 Current consumption when non accessed i 2 2 Current consumption when non accessed ii when CLKOUT OFF when CLKOUT 32 768kHz Condition A Condition fscL 0 Hz Ta 25 C CLKOUT OFF fscL 0 Hz Ta 25 C CLKOUT 32 768 kHz CL 30 pF IDDIKAJ Current consumption yA Current consumption uA IDD32KIUAJ CL 0 pF ege Supply Voltage VDDIV Supply Voltage Vop V Page 7 ETM12E 01 RX 8564 LC EPSON TOY M 10 External connection example o SCL l C BUS Master o SDA VDD 8564 SLAVE ADRS 1010001 SDAQ GND d Pull
15. the transmitter When the Master is the receiver if the Master does not send an ACK signal in response to the last byte sent from the slave that indicates to the transmitter that data transfer has ended At that point the transmitter continues to release the SDA and awaits a STOP condition from the Master 13 6 5 Slave address The lC bus device does not include a chip select pin such as is found in ordinary logic devices Instead of using a chip select pin slave addresses are allocated to each device All communications begin with transmitting the START condition slave address R W specification The receiving device responds to this communication only when the specified slave address it has received matches its own slave address Slave addresses have a fixed length of 7 bits This RTC s slave address is 1010 001 An R W bit above is added to each 7 bit slave address during 8 bit transfers Slave address R W bit Transfer data bit7 bite bit5 bit4 bit3 bit2 bi bit 0 Read A3h 0 0 0 0 1 1 Read Write A2h l 0 Write Page 34 ETM12E 01 RX 8564 LC EPSON TOY M 13 6 6 DC bus protocol In the following sequence descriptions it is assumed that the CPU is the master and the 8564 is the slave 1 Address specification write sequence Since the 8564 includes an address auto increment function once the initial address has
16. up Registor tr R Cgus l c BUS device Page 8 ETM12E 01 RX 8564 LC EPSON TOY M 11 Application notes 1 Notes on handling This module uses a C MOS IC to realize low power consumption Carefully note the following cautions when handling 1 Static electricity While this module has built in circuitry designed to protect it against electrostatic discharge the chip could still be damaged by a large discharge of static electricity Containers used for packing and transport should be constructed of conductive materials In addition only soldering irons measurement circuits and other such devices which do not leak high voltage should be used with this module which should also be grounded when such devices are being used 2 Noise If a signal with excessive external noise is applied to the power supply or input pins the device may malfunction or latch up In order to ensure stable operation connect a filter capacitor preferably ceramic of greater that 0 1 uF as close as possible to the power supply pins between VDD and GNDs Also avoid placing any device that generates high level of electronic noise near this module Do not connect signal lines to the shaded area in the figure shown in Fig 1 and if possible embed this area in a GND land 3 Voltage levels of input pins When the input pins are at the mid level this will cause increased current consumption and a reduced noise margin
17. 1 If this bit s value is 1 when read this RTC s data is ignored in which case all registers should be initialized before being used 1 A 1 is set to this VL flag during initial power on from 0 V Since the value of other registers is undefined at this time be sure to reset all registers before using them 2 When recovering from backup mode read this VL flag and if its value is 1 be sure to initialize the registers before using them 3 When initializing be sure to clear this VL flag to zero to prepare for the next voltage detection 4 This VL flag was designed to provide a voltage drop warning after the voltage of the backup battery or other devices has gradually dropped and it is not designed to respond to sharp fluctuations in voltage due to power supply chatter etc 1 VL 1 2 VL 0 3 VL24 VDD VLOW GND 1 VL 1 as result of initial supplv of power 2 When the power supply is low but voltage not dropping to Low VL remains at 0 with no change 3 When the power supply is low and voltage dropping below Low VL becomes 1 The value of the VL bit in 2 and 3 need to be zero cleared in 1 5 This VL flag is cleared via a write operation regardless of data Be sure to read this flag s value before writing to this register RX 8564 LC EPSON TOYOCOM 13 1 4 Calendar counter Reg 05 h 07 h 08 h Address h bit7 bite bit5 bit4 bits b
18. 1 and TDO bits are set and used e When this down counter s count value changes from 01h to 00h when TF bit 1 or when the INT pin is at low level L it indicates that a fixed cycle timer interrupt event has occurred e The current countdown status can be checked by reading this register However since the read data is not held the data may be changing to obtain accurate data the countdown status should be read twice and then compared For details see 9 2 Fixed cycle Timer Interrupt Function Page 16 ETM12E 01 RX 8564 LC EPSON TOVOCOM 13 1 9 CLKOUT output register Reg OD h Address h bit7 bite bit5 bit4 bits bit2 bit bito CLKOUT frequency This register is used to control clock output via the CLKOUT output pin This register is valid only when the CLKOE input pin is at high level at which time clock output is enabled or disabled stopped depending on the settings in this register When the CLKOE input pin is at low level CLKOUT is at low level regardless of the settings in this register 1 FE bit Frequency output Enable When this register is valid when CLKOE is at high level it is used to control the CLKOUT pin s output status When the FE bit value is 1 the CLKOUT pin is in output mode The content being output at that time is the frequency specified via the FD1 and FDO bit When the FE bit value is 0 the CLKOUT pin is output STOP mode low level
19. 2 FD1 FDO bits A combination of the FD1 and FDO bits is used to select the frequency to be output 3 CLKOUT output based on various settings CLKOE pin CLKOUT pin input output 32768 Hz Output C MOS Se m n E X don t care During initial power on from 0 V 1 is set to the FE bit by the power on reset function and the FD1 and FDO bits are reset to zero Consequently 32 768 kHz output can be obtained from the CLKOUT output pin by setting the CLKOE input pin to high level Note Re CLKOUT output operation when STOP bit value is 1 Note with caution that when the STOP bit value is 1 output via CLKOUT may be stopped depending on the selected frequency 1 When 32 768 kHz output has been selected output continues at 32 768 kHz 2 When any other frequency has been set 1024Hz 32Hz or 1Hz CLKOUT output is stopped Page 17 ETM12E 01 RX 8564 LC EPSON TOVI M 13 2 Fixed cvcle Timer Interrupt Function The fixed cvcle timer interrupt function generates an interrupt event periodicallv at anv fixed cvcle set between 244 14 us and 255 minutes There are two operation modes level interrupt mode whereby the operation ends after one time and repeated interrupt mode whereby the operation is automatically repeated When either of these interrupt events occurs the event s occurrence is indicated by the 1 value set to the TF bit and by the low level L status of the INT pin 13 2 1 Overview of
20. A L output current OL VoL 0 4 V VDD 5 V output curre INT OL L output current b VoL 0 4 V VDD 2 5 V output curre CLKOUT OL H output current OH VoH 4 6 V VDD 5 V output curre CLKOUT OH 4 d Leakage current ie Vo VDD or GND Ta 25 C Low voltage detection Ta 20 C to 70 C cS gt SE gt Q Z F 5 a lt 0 3 x VDD 0 7 x VDD VDD 0 5 3 gt 3 gt 3 gt gt Ta 40 C to 85 C t 3 Page 5 ETM12E 01 RX 8564 LC EPSON TOYO M 8 2 AC electrical characteristics Unless otherwise specified GND 0V VDD 1 8Vt05 5V Ta 40 C to 85 C Taw fej e l e LEE II pap ou Deme ea p mae uw fel E GC SE and START condition tale E E 2 o o SCL L time SCL H time tHIGH Timing chart t 7 7 2 t a o START BIT 6 STOP START Protocol CONDITION CONDITION CONDITI S A6 S 1SU STA 1 fscL tSU STA Lg A aot Se DM DAT THD DAT Note IC access time between a START and a START condition or between a START and a STOP condition to this device must be less than one second Page 6 ETM12E 01 RX 8564 LC EPSON TOY M 9 Reference data 1 Example of frequency and temperature characteristics Finding the frequency stability 0r 425 0 MP 1 Frequency and temperature characteristics can be x10 a 0 035 x 10 Tvp approximated using
21. E bit to prevent hardware interrupts from occurring inadvertently while entering settings 1 Alarm registers Reg 09 h to OC h The hour minute date or day when an alarm interrupt event will occur is set using this register and the AE bit When the settings made in the alarm registers match the current time the AF bit value is changed to 1 At that time if the AIE bit value has already been set to 1 the INT pin goes low AE bit 1 When the AE bit value is 1 the data concerning the setting in question is ignored and is not subject to any comparison that would trigger an alarm interrupt To exclude a setting from possibly triggering an alarm interrupt write 1 to the AE bit in the register corresponding to the setting in question Example To leave hour minute and day of week weekday settings as possible alarm interrupt triggers while excluding only the day setting from being a possible alarm interrupt trigger Write 80h AE 1 to the register used for the day setting register the DAY Alarm register Reg OB h 2 If all four AE bits have a value of 1 no alarm interrupt events will occur 2 AF bit Alarm Flag This is a flag bit that retains the result when an alarm interrupt event has been detected When this flag bit value is already set to 0 occurrence of an alarm interrupt event changes it to 1 AF Data Description The AF bit is cleare
22. For details see 9 2 Fixed cycle Timer Interrupt Function 2 AF bit Alarm Flag This is a flag bit that retains the result when an alarm interrupt event has been detected When an alarm interrupt event occurs this bit s value changes from O to 1 For details see 9 3 Alarm Interrupt Function 3 TF bit Timer Flag This is a flag bit that retains the result when a fixed cycle timer interrupt event has been detected When a fixed cycle timer interrupt event occurs this bit s value changes from O to 1 For details see 9 2 Fixed cycle Timer Interrupt Function 4 AIE bit Alarm Interrupt Enable This bit sets the operation of the INT interrupt signal when an alarm interrupt event has occurred the AF bit value changes from 0 to 1 When a 1 is written to this bit occurrence of an interrupt event causes a low level interrupt signal to be output from INT pin Writing O to this bit prohibits low level output from the INT pin For details see 9 3 Alarm Interrupt Function 5 TIE bit Timer Interrupt Enable This bit sets the operation of the INT interrupt signal when a fixed cycle interrupt event has occurred the TF bit value changes from O to 1 When a 1 is written to this bit occurrence of an interrupt event causes a low level interrupt signal to be output from INT pin Writing O to this bit prohibits low level output from the INT pin For details see 9 2 Fixed cy
23. Initialize Control 1 register e Initialize the Control 1 register Reg 00 h e Be sure to write 0 to the two TEST bits e Initialize the Control 2 register Reg 01 h Write 0 to the AIE and TIE bits to prevent output of unintended interrupts Initialize Control 2 register e Set Year Month Day day of week hour minute second Reg 02 h to 08 h For current time setting refer to Write to clock and calendar below Set current time e Set the alarm interrupt function Reg O9 h to OC h If the alarm interrupt function is not being used we recommend writing 1 to all four AE bits Set alarm interrupt e Set the CLKOUT output pin s output status Reg OD h Since the initial power on setting is output 32 768 kHz clock write O to the FE bit to stop output Set CLKOUT output e Set the timer interrupt function Reg OE h to OF h Set timer interrupt If the timer interrupt function is not used write 0 to the TE bit The address auto increment function can be used to set continuous writing Go to next process from Reg O0 h to OF h during initialization In such cases be sure to write 1 to the STOP bit to stop the clock before starting the continuous write operation and write O to the STOP bit to start the clock once initialization is completed 2 Example of initial power on processing Initial power on processing Wait until the in
24. RM0403 3 E01 G EPSON TOYOCOM Application Manual Real Time Clock Module RX 8564LC Model Product Number RX 8564LC Q418564C0xxxx00 EPSON TOYOCOM CORPORATION NOTICE e The material is subject to change without notice e Anv part of this material mav not be reproduced or duplicated in anv form or anv means without the written permission of EPSON TOVOCOM e The information applied circuit program usage etc written in this material is just for reference EPSON TOYOCOM does not assume any liability for the occurrence of infringing any patent or copyright of a third party This material does not authorize the licensing for any patent or intellectual copyrights e Any product described in this material may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export licence from the Ministry of International Trade and industry or other approval from another government agency e These products are intended for general use in electronic equipment When using them in specific applications that require extremely high reliability such as applications stated below it is required to obtain the permission from EPSON TOYOCOM in advance Space equipment artificial satellites rockets etc Transportation vehicles and related automobiles aircraft trains vessels etc Medical instruments to sustain life Submarine transm
25. T pin goes to low level and an event occurs 1 This bit is invalid after a 1 has been written to it 0 Fixed cycle timer interrupt events are not detected Read Fixed cycle timer interrupt events are detected Result is retained until this bit is cleared to zero a RX 8564 LC EPSON TOV M 6 TIE bit Timer Interrupt Enable This bit is used to control output of interrupt signals from the INT pin when a fixed cycle timer interrupt event has occurred When a 1 is written to this bit occurrence of an interrupt event causes a low level interrupt signal to be output from INT pin When a 0 is written to this bit output from the INT pin is prohibited disabled TIE Data Description 1 When a fixed cycle timer interrupt event occurs an interrupt signal is not generated or is canceled INT status remains Hi Z 2 When a fixed cycle timer interrupt event occurs the interrupt signal is canceled INT status changes from low to Hi Z Write Read When a fixed cycle timer interrupt event occurs an interrupt signal is generated INT status changes from Hi Z to low Level interrupt mode single shot operation If the TIE bit value is changed from O to 1 without first canceling the interrupt event the INT pin immediately goes to low level 13 2 3 Fixed cycle timer interrupt interval example The combination of the source clock settings settings in TD1 and TDO and fixe
26. T pin is not canceled The TF bit value is held until it is directly cleared to 1 i EN i E zero ki Rd TE bit fil AK i ers o i D 4 TIE bit o N Bee ee Bel EE L After the TF bitis cleared to zero the Hi z INT output 4 SE A E JINT pin is setto Hi Z mode regardless Nope H i of the TE bits value L N LE Sg NE N m rs IN ji Lj B When the TF bit is cleared to i H zero INT is canceled jon TF bit in o ww BAY Fe o B 1st period Ne 2nd period e hand Internal interrup 1 01h00 jb 01h 00 1 When TE 0 the countdown is stopped processing Wi Onn i i ee RE x The fixed cycle timer function starts the countdown starts when the TE bit value changes from 0 to 1 x Before starting the fixed cycle timer interrupt function each time be sure to write a value preset value Reg OF h as the timer s down counter value when TE 0 j RTC s internal operation gt Write operation x Before starting the fixed cycle timer interrupt function each time be sure to write a value preset value Reg OF h as the timer s down counter value when TE 0 Note Note with caution that the preset value must be set or reset to enable correct operation x Before entering operation settings we recommend first clearing the TE bit to 0 and then clearing the TF and TIE bits to O in that order so that all control related bits are zero cleared set to operation stop mode to
27. and can impair the functioning of the device Therefore try as much as possible to apply the voltage level close to VDD or GND 4 Handling of unused pins Since the input impedance of the input pins is extremely high operating the device with these pins in the open circuit state can lead to unstable voltage level and malfunctions due to noise Therefore pull up or pull down resistors should be provided for all unused input pins 2 Notes on packaging 1 Soldering heat resistance If the temperature within the package exceeds 4260 C the characteristics of the crystal oscillator will be degraded and it may be damaged The reflow conditions within our reflow profile is recommended Therefore always check the mounting temperature and time before mounting this device Also check again if the mounting conditions are later changed See Fig 2 profile for our evaluation of Soldering heat resistance for reference 2 Packaging equipment This product uses a molded package whose back contains glass Therefore it is possible for shocks during packaging to cause product breakage depending on the packaging machinery and conditions Please be sure to check that the load placed on products during packaging is as low as possible low speeds during loading onto the substrate low chuck forces etc before using packaging equipment Carry out the same checks when changing packaging conditions The presence of foreign objects between this product and the pa
28. art the fixed cycle timer interrupt function again The status during a countdown can be checked by reading this register However since the read data is not held the data may be changing to obtain accurate data the countdown status should be read twice and then compared 4 TE bit Timer Enable This bit enables operation of the of the fixed cycle timer interrupt function to start TE Data Description 0 Stops fixed cycle timer interrupt function Write Read 1 Starts fixed cycle timer interrupt function 5 TF bit Timer Flag This is a flag bit that retains the result when a fixed cycle timer interrupt event is detected If it was already cleared to zero this value changes from 0 to 1 when an event occurs and the new value is retained TF Data Description The TF bit is cleared to zero to cancel the interrupt event to prepare for the next event detection Note Even after the interrupt event has been canceled the fixed cycle timer function operates continuously as long as the TE bit Timer Enable value is 1 Write 0 Level interrupt mode single shot operation 1 Clearing the TF bit to zero cancels the low level status of the INT pin the INT pin goes to Hi Z status 2 When the TE bit value remains 1 the timer s down counter continues to count down and when the counter value goes form 01h to 00h the TF bit value is again changed to 1 the IN
29. ave address matches the slave address in the received data In either case the data is transferred via the SCL line at a rate of one bit per clock pulse 13 6 2 Svstem configuration All ports connected to the FC bus must be either open drain or open collector ports in order to enable AND connections to multiple devices SCL and SDA are both connected to the VDD line via a pull up resistance Consequently SCL and SDA are both held at high level when the bus is released when communication is not being performed VDD SDA SCL Master Slave Master Slave Transmitter Transmitter Transmitter Transmitter Receiver Receiver Receiver Receiver CPU etc 8564 Other I C bus device Any device that controls the data transmission and data reception is defined as a Master and any device that is controlled by a master device is defined as a Slave The device transmitting data is defined as a Transmitter and the device receiving data is defined as a receiver In the case of this RTC module controllers such as a CPU are defined as master devices and the RTC module is defined as a slave device When a device is used for both transmitting and receiving data it is defined as either a transmitter or receiver depending on these conditions Page 32 ETM12E 01 RX 8564 LC EPSON TOY M 13 6 3 Starting and stopping 12C bus communications START Repeated START RESTART STOP condition co
30. been specified the 8564 increments by one byte the receive address each time data is transferred 1 CPU transfers start condition S 2 CPU transmits the 8564 s slave address with the R W bit set to write mode 3 Check for ACK signal from 8564 4 CPU transmits write address to 8564 5 Check for ACK signal from 8564 6 CPU transfers write data to the address specified at 4 above 7 Check for ACK signal from 8564 8 Repeat 6 and 7 if necessary Addresses are automatically incremented 9 CPU transfers stop condition P TT sg EE S Slave address 0 0 i Address i 0 l Data l 0 Data E 0 P RW 4 A i 4 ACK signal from 8564 A e 8 4 e m 9 al 2 Address specification read sequence After using write mode to write the address to be read set read mode to read the actual data 1 CPU transfers start condition S 2 CPU transmits the 8564 s slave address with the R W bit set to write mode 3 Check for ACK signal from 8564 4 CPU transfers address for reading from 8564 b Check for ACK signal from 8564 6 CPU transfers RESTART condition Sr in which case CPU does not transfer a STOP condition P 7 CPU transfers 8564 s slave address with the R W bit set to read mode 8 Check for ACK signal from 8564 from this point on the CPU is the receiver and the 8564 i
31. but even in such cases the series of operations from transmitting the START condition to transmitting the STOP condition should still occur within 1 seconds If this series of operations requires 1 seconds or longer the FC bus interface will be automatically cleared and set to standby mode by this RTC module s bus timeout function Note with caution that both write and read operations are invalid for communications that occur during or after this auto clearing operation When the read operation is invalid all data that is read has a value of 1 Restarting of communications begins with transfer of the START condition again 4 When communicating with this RTC module wait at least 1 3 us see the tBUF rule between transferring a STOP condition to stop communications and transferring the next START condition to start the next round of communications STOP START condition condition SCL 1 3 us Min Page 33 ETM12E 01 RX 8564 LC EPSON TOY M 13 6 4 Data transfers and acknowledge responses during I2C BUS communications 1 Data transfers Data transfers are performed in 8 bit 1 byte units once the START condition has occurred There is no limit on the amount bytes of data that are transferred between the START condition and STOP condition However the transfer time must be no longer than 1 seconds The address auto increment function operates during both write and read operations After address F
32. ce clock e Select using a combination of TD1 and TDO bit values 3 e Set down counter s initial value Reg OF h Note Be sure to set or reset the down counter s initial value each time Write 1 to the TE bit to start the timer interrupt function Note Before starting the timer interrupt function be sure to set or reset the down counter s initial value see 3 above Page 31 ETM12E 01 RX 8564 LC EPSON TOY M 13 6 Reading Writing Data via the I C Bus Interface 13 6 1 Overview of IZC BUS The IC bus supports bi directional communications via two signal lines the SDA data line and SCL clock line A combination of these two signals is used to transmit and receive communication start stop signals data transfer signals acknowledge signals and so on Both the SCL and SDA signals are held at high level whenever communications are not being performed The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level During data transfers data changes that occur on the SDA line are performed while the SCL line is at low level and on the receiving side the data is output while the SCL line is at high level The lC bus device does not include a chip select pin such as is found in ordinary logic devices Instead of using a chip select pin slave addresses are allocated to each device and the receiving device responds to communications only when its sl
33. ckaging substrate may result in product breakage Guard against introduction of foreign objects during packaging Also carry out measures to eliminate static electricity during packaging of and operations with this product 3 Ultrasonic cleaning Depending on the usage conditions there is a possibility that the crystal oscillator will be damaged by resonance during ultrasonic cleaning Since the conditions under which ultrasonic cleaning is carried out the type of cleaner power level time state of the inside of the cleaning vessel etc vary widely this device is not warranted against damage during ultrasonic cleaning 4 Mounting orientation This device can be damaged if it is mounted in the wrong orientation Always confirm the orientation of the device before mounting 5 Leakage between pins Leakage between pins may occur if the power is turned on while the device has condensation or dirt on it Make sure the device is dry and clean before supplying power to it 6 Use of adhesive after packaging product This product uses a molded package whose back contains glass Please check that use of the adhesive does not cause problems before adopting any adhesive as a measure to reinforce the packaging for your product Fig 1 Example GND Pattern Fig 2 Reference profile for our evaluation of Soldering heat resistance RX 8564 LC Temperature C Oe P 260 C Max 1 5 C s
34. cle Timer Interrupt Function Page 13 ETM12E 01 RX 8564 LC EPSON TOY M 13 1 3 Clock counter Reg 02 h to 04 h Address hl bit7 bit6 bit i bit4 bits bit2 bit bito Seconds Minutes Hours The clock counter counts seconds minutes and hours e The data format is BCD format For example when the seconds register value is 0101 1001 it indicates 59 seconds When overwriting time data we recommend setting 1 to the STOP bit to stop the clock before overwriting This prevents unintentional carry operations from occurring while overwriting data Note with caution that writing non existent time data may interfere with normal operation of the clock counter 1 Seconds register Reg 02 h This counter counts seconds Count values are updated as 00 seconds 01 second 02 to 59 seconds 00 seconds 01 second etc in that order 2 Minutes register Reg 03 h This counter counts minutes Count values are updated as 00 minutes 01 minute 02 to 59 minutes 00 minutes 01 minute etc in that order 3 Hours register Reg 04 h The Hours counter uses a 24 hour clock Count values are updated as 00 hours 01 hour 02 to 23 hours 00 hours 01 hour etc in that order 4 VL bit Voltage Low Flag This is a flag bit that retains the result when detecting low voltage When the power source s voltage drops below VLOWIVT this flag is set to
35. d Branch Office French Branch Office ASIA EPSON CHINA CO LTD 23F Beijing Silver Tower 2 North RD DongSangHuan ChaoYang District Beijing China Phone 86 10 6410 6655 Fax 86 10 6410 7319 http www epson com cn Shinghai Branch Phone 86 21 5423 5577 Fax 86 21 5423 4677 EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai Hong kong Phone 852 2585 4600 Fax 852 2827 2152 http www epson com hk EPSON ELECTRONIC TECHNOLOGY DEVELOPMENT SHENZHEN CO LTD 12 F Dawning Mansion 12 Keji South Road Hi Tech Park Shenzhen China Phone 86 755 26993828 Fax 86 755 26993838 EPSON TAIWAN TECHNOLOGY amp TRADING LTD 14F No 7 Song Ren Road Taipei 110 Phone 886 2 8786 6688 Fax 886 2 8786 6660 http www epson com tw EPSON SINGAPORE PTE LTD No 1 HarbourFront Place 03 02 HarbourFront Tower One Singapore 098633 Tel 65 6 586 5500 Fax 65 6 271 3182 http www epson com sg SEIKO EPSON CORPORATION KOREA Office 50F KLI 63 Building 60 Voido dong Voungdeungpo Ku Seoul 150 763 Korea Phone 82 2 784 6027 Fax 82 2 767 3677 http www epson device co kr 2F Grand Bldg 457 4 Songjeong dong Gumi City Gyongsangbuk Do 730 090 Korea Phone 82 54 454 6027 Fax 82 54 454 6093 Gumi Branch Office EPSON TOYOCOM CORPORATION QD SALES ENGINEERING GROUP Electronic devices information on WWW server http www epsontovocom co jp 1960 E Grand Ave 2nd Flo
36. d cycle timer countdown setting Reg C setting sets the fixed cycle timer interrupt interval as shown in the following examples Source clock Timer Counter 4096 Hz 1 Hz 1 60 Hz setting When seconds When minutes setting is updated setting is updated TD1 0 1 0 TD1 0 1 1 e Fixed cycle timer interrupt time error and fixed cycle timer interrupt interval time A fixed cycle timer interrupt time error is an error in the selected source clock s _ interval time Accordingly the fixed cycle timer interrupt s interval one cycle falls within the following range in relation to the set time Fixed cycle timer interrupt s interval Fixed cycle timer interrupt s set time source clock interval to fixed cycle timer interrupt set time x Fixed cycle timer interrupt s set time Source clock setting x Countdown timer setting for fixed cycle timer x The time actually set to the timer is adjusted by adding the time described above to the communication time for the serial data transfer clock used for the setting Page 22 ETM12E 01 RX 8564 LC EPSON TOY M 13 2 4 Diagram of fixed cvcle timer interrupt function 13 2 4 1 Operation example of level interrupt mode TI TP 2 0 e After an interrupt event has occurred this function operates only once Start of fixed cycle timer operation 6 Even if the TE bit is cleared to zero the TF bit value is held as 1 Also the IN
37. d to zero to prepare for the next status detection 0 Clearing this bit to zero enables AIRQ low output to be canceled AIRQ Write remains Hi Z when an alarm interrupt event has occurred 1 This bit is invalid after a 1 has been written to it 0 Alarm interrupt events are not detected Read Alarm interrupt events are detected x Result is retained until this bit is cleared to zero Page 26 ETM12E 01 RX 8564 LC EPSON TOV M 3 AIE bit Alarm Interrupt Enable This bit is used to control interrupt signal output from the INT pin when an alarm interrupt event has occurred Writing 1 to this bit causes a low level interrupt signal to be output from the INT pin when an interrupt event occurs When a 0 is written to this bit output from the INT pin is prohibited disabled AIE Data Description 1 When an alarm interrupt event occurs an interrupt signal is not generated or is canceled INT status remains Hi z 2 When an alarm interrupt event occurs the interrupt signal is canceled INT status changes from low to Hi z GEES When an alarm interrupt event occurs an interrupt signal is generated INT status changes from Hi z to low x If the AIE bit value is changed from 0 to 1 without first canceling an interrupt event i e if the AF bit value remains 1 the INT pin is immediately set to low level L x To detect when an alarm interrupt event has occu
38. down counter 3 The following processing is executed after an event is triggered by the countdown reaching a count value of 0 xi The TF Timer Flag bit value becomes 1 2 When the TIE Timer Interrupt Enable bit value becomes 1 the INT output pin s status changes from Hi z to L After the INT output pin s status changes from Hi z to L the INT status is either held at low level or automatically cleared depending on the TI TP bit s setting from the operation mode level interrupt mode or repeated interrupt mode 9 The timer s down counter automatically returns to the preset value and then the countdown operation is repeated When the TE bit value is 1 countdown operation of the timer s down counter will be repeated regardless of the operation mode or of any event that has occurred 4 When the TE bit is cleared from 1 to 0 the fixed cycle timer interrupt function stops 1 The TF bit value remains 1 until it is cleared to zero even if the fixed cycle timer function has been stopped 2 The timer s down counter value becomes invalid once the fixed cycle timer function has been stopped When the fixed cycle timer interrupt function is stopped the timer s down counter value and the preset value both become invalid The preset value must be written again when TE 0 in order to start the fixed cycle timer interrupt function again x Operation
39. e that an event has occurred x For details see 13 3 Alarm Interrupt Function 4 32 768 kHz output function The 32 768 kHz clock signal with precision equal to that of the on chip crystal osillator can be output as C MOS output via the CLKOUT pin If a different frequency is required 32 768 kHz 1024 Hz 32 Hz or 1 Hz can be selected x For details see 13 1 9 CLKOUT output register Page 10 ETM12E 01 RX 8564 LC EPSON TOYOCOM 12 2 Register table RSR Control 2 EE SS RER SS EE Ce f eenn fe e e e Ce faem e e rep Note During the initial power on from 0 V and if the value of the VL bit is 1 when the VL bit is read be sure to initialize all registers before using them When doing this be careful to avoid setting incorrect data as the date or time as timed operations cannot be guaranteed if incorrect date or time data has been set 1 During the initial power on from 0 V the power on reset function sets 1 to the VL bit Since the value of other registers is undefined at this time be sure to reset all registers before using them 2 During the initial power on from 0 V the power on reset function sets 1 to the FE bit and the FD1 and FDO bits are reset to O H the CLKOE input pin is at high level H output from the CLKOUT output pin is at 32 768 kHz 3 The two TEST bits for address 00 Control 1 are for use by Seiko Epson Corporation When initializing be sure to wr
40. example Operation example during repeated interrupt mode and when preset value is 5 05h 4 TE bit Timer function is ON ne Timer Enable NEP sees 1 Timer function is OFF L l L Timer s down counter 0 0 0 l Timer Register 543215432154321 543 REE AE gd TITT ITFI i e EE ak Se Fixed cycle timer ll Y Y Y Countdown is stopped interrupt Source Internal event occurs at clock I Count value and preset v part Period Period Period AE are invalid INT output poe Open drain output lt gt x When TIE 2 1 output is at low level only during tRTN period When the TE bit is changed to 1 the countdown starts from the preset value which is 5 05h in this example Page 19 ETM12E 01 RX 8564 LC EPSON TOY M 13 2 2 Related registers for function of timer interrupts Address H Function bit7 bite 1 bits 1 bit4 bits bit2 biti 01 Control 2 OE Timer control OF Timer x Before starting the fixed cycle timer interrupt function each time be sure to write a value preset value Reg OF h as the timer s down counter value when TE 0 Note Note with caution that the preset value must be set or reset to enable correct operation Before entering operation settings we recommend first clearing the TE bit to 0 and then clearing the TF and TIE bits to O in that order so that all control related bits are zero cleared set to operation stop
41. fixed cycle timer interrupt function e The fixed cycle timer interrupt function is used with several combinations of settings 1 Operation mode setting level interrupt mode or repeated interrupt mode 2 Fixed cycle timer operation period setting period countdown reference cycle x count value 3 Setting as to whether to output at low level an interrupt signal from the INT output pin after a specified amount of operation time has elapsed e When operation of the fixed cycle timer starts TE 0 gt 1 various events occur after the specified time has elapsed 1 The TF Timer Flag bit value which indicates when a fixed cycle timer interrupt event has occurred changes from 0 to 1 2 When the TIE Timer Interrupt Enable bit value is 1 the INT output pin status changes from Hi Z to L 1 Overview of level interrupt mode TI TP bit 0 Once an interrupt event has occurred the operation ends after one iteration However if only the TF bit is cleared to zero without stopping operation of the fixed cycle timer TE bit value remains 1 note with caution that an interrupt event will occur during the next timer cycle period If an interrupt event occurs during level interrupt mode the INT output goes to low level The low level output is maintained as it is until the TF bit is cleared to zero When TIE 1 Example of INT operation period TF 1 gt 0 2 Overview of repeated interrupt
42. ge of century When the year digit data overflows from 99 to 00 this bit is set By presetting it to O while still in the 20th century it will be set in year 2000 but in fact the first year in the 21 century should be 2001 13 1 5 Day counter Reg 6 h Address h bit7 bite bit5 bit4 bits bit2 bit bito me Weekdavs x x e The day of the week is indicated by 3 bits bit 0 to bit 2 Weekdays l bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Day x x x x x 0 0 0 Sunday x x x x x 0 l 0 1 Monday x x x x x 0 1 0 Tuesday Write Read x ie ae ee x 1 Wednesday x x x x x 1 0 0 Thursday x x x x xli ee Friday x x x x x 1 1 0 Saturday Note with caution that any settings other than the seven listed above may prevent normal operation Page 15 ETM12E 01 RX 8564 LC EPSON TOVOCOM 13 1 6 Alarm registers Reg 09 h to OC h Address h it7 bite bit5 i bit 09 Minute Alarm AE 40 20 10 e 4 2 1 0A Hour Alarm AE x 20 10 8 4 2 1 0B Day Alarm AE x 20 10 8 4 2 1 0C Weekday Alarm AE x x x x 4 2 1 The AIE bit and AF bit can both be set or used when using alarm interrupt function to set interrupt events for dates days hours minutes etc When the current time matches the settings in the above alarm registers the AF bit s value is 1 and the INT pin s statu
43. h incrementation goes to address Oh Updating of data on the transmitter transmitting side s SDA line is performed while the SCL line is at low level The receiver receiving side receives data while the SCL line is at high level Data is valid Data can be when data line is changed stable ra 4 Note with caution that if the SDA data is changed while the SCL line is at high level it will be treated as a START RESTART or STOP condition 2 Data acknowledge response ACK signal When transferring data the receiver generates a confirmation response ACK signal low active each time an 8 bit data segment is received If there is no ACK signal from the receiver it indicates that normal communication has not been established This does not include instances where the master device intentionally does not generate an ACK signal Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line the transmitter releases the SDA line and the receiver sets the SDA line to low acknowledge level SCL from Master 1 2 8 9 SDA from transmitter sending side SDA from receiver receiving Low active side ACK signal After transmitting the ACK signal if the Master remains the receiver for transfer of the next byte the SDA is released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line Data transfer resumes when the Master becomes
44. it2 bit bito Days Months Century Years e The auto calendar function updates all dates months and years from January 1 2001 to December 31 2099 e The data format is BCD format For example a date register value of 0011 0001 indicates the 31st Note with caution that writing non existent date data may interfere with normal operation of the calendar counter 1 Day register Reg 05 h This is the date counter Updating of this counter varies depending on the month A leap year is set whenever the year value is a multiple of four such as 04 08 12 88 92 or 96 In February of a leap year the counter counts dates from 01 02 03 to 28 29 01 etc Days Month Date update pattern 1 3 5 7 8 10 or 12 01 02 03 30 31 01 Write Read 4 6 9 or 11 01 02 03 30 01 02 February in normal year 01 02 03 28 01 02 February in leap year 01 02 03 28 29 01 2 Months Century register Reg 07 h e This is the month counter It is updated in annual cycles of regularly ordered months January February March etc 3 YEAR register Reg 08 h This is the year counter It is updated in 100 year cycles of regularly ordered years 00 01 02 to 99 etc Any year that is a multiple of four 04 08 12 88 92 96 etc is handled as a leap year 4 C bit Century bit e This bit indicates chan
45. ite 0 Afterward be sure to write 0 whenever writing to these bits This device s operations are not guaranteed if 1 has been set to any of these bits 4 All bits marked with 0 should have a value of 0 after initialization zb All bits marked with x are read only bits whose value when read is undefined Be sure to mask these bits after they are read RX 8564 LC EPSON TOY M 13 Description of Functions 13 1 Description of registers 13 1 1 Control register 1 Reg 00 h Address H Function bit7 bit6 bits bit4 bits bit2 bit bito o Control 1 0 This register is used to control stopping and starting of the clock function calendar function and other functions 1 TEST bits bit 7 and bit 3 These two TEST bits are for use by Seiko Epson Corporation When initializing be sure to write 0 Afterward be sure to write 0 whenever writing to these bits This device s operations are not guaranteed if 1 has been set to any of these bits 2 STOP bit The STOP bit is used to stop functions such as the clock calendar alarm and timer Writing 1 to the STOP bit stops operation of the clock calendar alarm timer etc 1 When the STOP bit 2 1 operations are restricted Do not use any settings other than the clock and calendar settings 2 When the STOP bit 2 1 output via CLKOUT may be stopped depending on the selected frequency Note this with caution
46. itters Power Stations and related Fire work equipment and security equipment traffic control equipment and others requiring equivalent reliability n this manual for EPSON TOYOCOM product code and marking will still remain as previously identified prior to the merger Due to the on going strategy of gradual unification of part numbers please review product code and marking as they will change during the course of the coming months We apologize for the inconvenience but we will eventually have a unified part numbering system for Epson Toyocom which will be user friendly RX 8564 LC EPSON TOYOCOM CONTENTS Nei TT 1 2 Block E Lef un EE 1 S Terminal des riptioti EE 2 3 1 Terminal connections czna as a en e retener ne tenetis 2 3 2 Pini FUNCHONS RA ERR UNIES ee Reo eR 2 4 External Dimensions Marking Layout sss 3 4 1 External Dimensions 2 0 cccccccccscssscesesssesesescecesesesessssscssssasesesesessssscsceceesesessseacscecaeeteneneneess 3 4 2 Marking Lay OUI cott te eot deti tete ended te et tu tutelae 3 5 Absolute Maximum Ratings sse 4 6 Recommended operating conditions sss 4 7 Frequency Characteristics e 4 Eege Eer 5 EE Te Ee 5 8 2 AC electrical characteristics sse tnter 6 9 Rielerernceredal asusta ettet led oe ste ur eee 7 10 External connection example sss 8 TISADBIICAUOH TOIBS occ tn tou eun MAS MA DUUM MA MM 9 12 Overview of Functions and
47. ndition condition SCL NC a Es N Nea ad Rape sf O Sr l SDA Y V i N d La 1s Max 1 START condition repeated START condition and STOP condition 1 START condition The SDA level changes from high to low while SCL is at high level 2 STOP condition e This condition regulates how communications on the I C BUS are terminated The SDA level changes from low to high while SCL is at high level 3 Repeated START condition RESTART condition n some cases the START condition occurs between a previous START condition and the next STOP condition in which case the second START condition is distinguished as a RESTART condition Since the required status is the same as for the START condition the SDA level changes from high to low while SCL is at high level 2 Caution points 1 The master device always controls the START RESTART and STOP conditions for communications 2 The master device does not impose any restrictions on the timing by which STOP conditions affect transmissions so communications can be forcibly stopped at any time while in progress However this is only when this RTC module is in receiver mode data reception mode SDA released 3 When communicating with this RTC module the series of operations from transmitting the START condition to transmitting the STOP condition should occur within 1 seconds A RESTART condition may be sent between a START condition and STOP condition
48. nge 1 0V to 5 5V at Ta 25 C e Low backup current 275 nA WP 3 V e 32 768 kHz clock frequency output C MOS output with output control Real time clock function Clock calendar function auto leap year correction function alarm interrupt function etc The I C BUS is a trademark of PHILIPS ELECTRONICS N V 1 Overview This module is an I C bus interface real time clock that has bult in 32 768 kHz crystal oscillator In addition to a calendar year month day weekday hour minute second function and a clock counter function this module s real time clock functions include an alarm function and a fixed cycle timer interrupt function The devices in this module are fabricated via a C MOS process for low current consumption which enables long term battery back up All of these many functions are implemented in a compact package which makes it suitable for various kinds of mobile telephones handy terminals and other small electronic devices 2 Block diagram 32 768 kHz 7 CRVSTAL Control 1 osc Voltage Detector Control 2 Seconds Minutes Hours DIVIDER Days Weekdays Month Century OUTPUT CONTROL Years CONTROL Minutes Alarm LOGIC Hour Alarm BC BUS DayAlarm INTERFACE Weekday Alarm CLKOUT frequency Timer Conte ADDRESS REGISTER Timer Page 1 ETM12E 01 RX 8564 LC EPSON TOYO M 3 Terminal description 3 1 Terminal connections
49. or El Segundo CA 90245 U S A High Tech Building 900 Yishan Road Shanghai 200233 China TOYOCOM U S A INC 617 East Golf Road Suite 112 Arlington Heights IL60005 U S A Phone 1 847 593 8780 Fax 1 847 593 5678 TOYOCOM EUROPE GmbH HEADQUARTER Bollenhoehe 5 40822 Mettmann Germany Phone 49 2104 91890 Fax 49 2104 918930 UK Office Unit 4 e space south 26 St Thomas Place Ely Cambridgeshir CB7 4EX England Phone 44 0 1353 644060 Fax 44 0 8704 583822 TOYOCOM ASIA PTE LTD No 1 Tannery Road 05 03 Cencon I Singapore 347719 Phone 65 6841 6311 Fax 65 6841 2886 TOYOCOM HONG KONG LTD Unit 11 amp 12 8 F Millennium City 378 Kwun Tong Road Kwun Tong Kowloon Hong Kong Phone 852 2409 9033 Fax 852 2409 9130 TOYOCOM SHANGHAI CO LTD High Tech Building 900 Yishan Road Shanghai 200233 China Phone 86 21 5423 4000 Distributor
50. ource clock has been selected is linked to updating of the internal clock s seconds setting Since the internal clock is linked to updating of the seconds setting if the timer is started at a clock time of 0 9 seconds the first countdown will occur only 0 1 second later The second and subsequent countdowns will occur at the correct time interval 2 The countdown when a 1 60 Hz source clock has been selected is linked to updating of the internal clock s minutes setting Since the internal clock is linked to updating of the minutes setting if the timer is started at a clock time of 50 seconds the first countdown will occur only 10 seconds later The second and subsequent countdowns will occur at the correct time interval Page 20 ETM12E 01 RX 8564 LC EPSON TOY M 3 Down counter for fixed cvcle timer Timer Register This register is used to set the default preset value for the counter Any count value from 1 01 h to 255 FFh can be set When the fixed cycle timer interrupt function is operating the down counter counts down one step per source clock cycle and when the count value goes from 01h to 00h an event such as changing the TF bit value to 1 occurs x When the fixed cycle timer function has been stopped when the TE bit value has been changed from 1 to 0 the timer s down counter value and preset value both become invalid x The preset value must be written again when TE 0 in order to st
51. prevent hardware interrupts from occurring inadvertently while entering settings 1 When the TE bit value is changed from 0 to 1 the fixed cycle timers countdown begins 2 A fixed cycle timer interrupt event occurs when the down counter value goes from 01h to 00h during a countdown in which the down counter s count value is decremented at each source clock cycle 3 When a fixed cycle timer interrupt event occurs the TF bit value is changed to 1 4 If the TIE bit 1 when a fixed cycle timer interrupt occurs TIRQ pin output goes low H the TIE bit 0 when a fixed cycle timer interrupt occurs TIRQ pin output remains Hi Z 5 During the period when the TF bit value is 1 following the occurrence of an interrupt event the TIE bit can be set to switch the INT pin to any status 6 As long as the TE bit value remains 1 the operation sequence countdown by timer s down counter 7 internal event processing loading of preset value countdown is repeated regardless of the operation mode etc However this operation sequence has no effect unless the TF bit has been cleared to zero f the TE bit value remains 1 and only the TF bit is cleared to zero the fixed cycle timer continues to operate note with caution that an interrupt event will occur the next time the counter value changes from 01h to 00h the TF bit will become 1 again and the INT pin status will be L 6 When the TF bit
52. rom CPU Page 35 ETM12E 01 EPSON TOVOCOM Application Manual AMERICA EPSON ELECTRONICS AMERICA INC HEADQUARTER 150 River Oaks Parkway San Jose CA 95134 U S A Phone 1 800 228 3964 Toll free 1 408 922 0200 Main Fax 1 408 922 0238 http www eea epson com Atlanta Office One Crown Center 1895 Phoenix Bivd Suite 348 Atlanta GA 30349 Phone 1 800 228 3964 Toll free 1 770 907 7667 Main 301Edgewater Place Ste 120 Wakefield MA 01880 U S A Phone 1 800 922 7667 Toll free 1 781 246 3600 Main Fax 1 781 246 5443 101 Virginia St Ste 290 Crvstal Lake IL 60014 U S A Phone 1 800 853 3588 Toll free 1 815 455 7630 Main Fax 1 815 455 7633 Boston Office Chicago Office El Segundo Office Phone 1 800 249 7730 Toll free 1 310 955 5300 Main Fax 1 310 955 5400 EUROPE EPSON EUROPE ELECTRONICS GmbH HEADQUARTER Riesstrasse 15 80992 Munich Germany Phone 49 0 89 14005 0 Fax 49 0 89 14005 110 http www epson electronics de Altstadtstrasse 176 51379 Leverkusen Germany Phone 49 0 2171 5045 0 Fax 49 0 2171 5045 10 Unit 2 4 Doncastle House Doncastle Road Bracknell Berkshire RG12 8PE England Phone 44 0 1344 381700 Fax 44 0 1344 381701 LP 915 Les Conqu rants 1 Avenue de I Atlantique Z A de Courtaboeuf 2 91976 Les Ulis Cedex France Phone 33 0 1 64862350 Fax 33 0 1 64862355 D sseldorf Branch Office UK amp Irelan
53. rred without having to set the INT pin to low level monitor the AF bit value to see if it changes from 0 to 1 while keeping the AIE bit value as 0 13 3 3 Examples of alarm settings 1 Basic information about alarm settings e Four parameters can be set as alarm objects minute hour day and date e Hour settings are based on a 24 hour clock e To exclude a setting from possibly triggering an alarm interrupt write 1 to the AE bit in the register corresponding to the setting in question x If all four AE bits have a value of 1 no alarm interrupt events will occur e Alarm interrupt events occur when conditions change to become conditions which trigger an alarm 2 Examples of alarm settings are listed below Reg 0C h Reg OB h Reg OA h Reg O9 h Weekday Day Hour Minute Alarm Alarm Alarm Alarm Weekday set Day set Hour set Minute set At 7 30 AM every G t AE bit 1 07h 30h Monday f k M M onday Weekday Day ignored 7 00 AM 30 Minute At 7 30 PM on the 15th D cede 15h 19h 30h of each month ignored y 15 days 7 00 PM 30 minutes At the top of each ADI AE bit 1 AE bit 1 00h hour one hour cycle ee Day ignored Hour ignored 00 minutes Page 27 ETM12E 01 RX 8564 LC EPSON TOY M 13 4 INT L Interrupt Output When Interrupt Function Operates 1 Setting interrupt events to occur in response to INT L interrupt output
54. s is low to indicate that an alarm interrupt event has occurred For details see 9 3 Alarm Interrupt Function 13 1 7 Timer setting register Reg OE h eee cum Dur ue Tue Der Tur Ter er Tu ji oE Timer control e This register is used to control the fixed cycle timer interrupt function e To use the fixed cycle timer interrupt function the TI TP bits Reg 01 hl timer register Reg OF hl and the TF and TIE bits are all set or used 1 TE bit Timer Enable This bit is used to control operation of the fixed cycle timer interrupt function When 1 is written to this bit the fixed cycle timer interrupt function starts operating When 0 is written to this bit the fixed cycle timer interrupt function stops operating x For details see 9 2 Fixed cycle Timer Interrupt Function 2 TD1 TDO bits Timer countDown interval select 1 0 These bits specify the fixed cycle timer interrupt function s countdown period source clock Four different periods can be selected via combinations of these two bit values x For details see 9 2 Fixed cycle Timer Interrupt Function 13 1 8 Down counter for fixed cycle timer Reg OF h Address h bit7 bite bit bit4 bits bit2 bit bito e This register is used to set the default preset value for the counter Any count value from 1 01 h to 255 FFh can be set e To use the fixed cycle timer interrupt function the TE TI TP TF TIE TD
55. s the transmitter 9 Data from address specified at 4 above is output by the 8564 10 CPU transfers ACK signal to 8564 11 Repeat 9 and 10 if necessary Read addresses are automatically incremented 12 CPU transfers ACK signal for 1 13 CPU transfers stop condition P 1 2 3 4 7 8 9 10 11 12 13 S Slave address 0 0 i Address O Sr Slave address 1 0 i Data 0 Data 1 P R W i R W t e 4 ACK from CPU ACK from 8564 3 Read sequence when address is not specified Once read mode has been initially set data can be read immediately In such cases the address for each read operation is the previously accessed address 1 1 CPU transfers start condition S 2 CPU transmits the 8564 s slave address with the R W bit set to read mode 3 Check for ACK signal from 8564 from this point on the CPU is the receiver and the 8564 is the transmitter 4 Data is output from the 8564 to the address following the end of the previously accessed address b CPU transfers ACK signal to 8564 6 Repeat 4 and 5 if necessary Read addresses are automatically incremented in the 8564 7 CPU transfers ACK signal for 1 8 CPU transfers stop condition P 1 e B 4 B e o 6 S i Slave address 1 0 Data 0 Data i 1 P EW 4 LEM 4 ACK from 8564 ACK f
56. teristics ict Unless otherwise specified GND 0 V 7 Frequency Characteristics ji aes a Item Comments Output frequency Ta 25 C Vpp 3 0 V Ta 25 C Vpp 1 8Vto5 5V Frequency precision Frequency voltage characteristics Frequency temperature characteristics Ta 20 C to 70 C VDD 3 0 V Reference at 25 C Ta 25 C Oscillation VDD 1 8V startup up time Ta 40 C to 85 C VDD 3 0V Aging Ta 25 C VDD 3 0 V first year 1 This difference is 1 minute by 1 month excluding offset 2 Includes variation in frequency during two rounds of reflow processing x Reflow processing is performed under conditions specified by Seiko Epson Corporation See the relevant specifications Page 4 ETM12E 01 RX 8564 LC EPSON TOYO M 8 Electrical Characteristics 8 1 DC characteristics Unless otherwise specified GND 0V VDD 1 8Vt05 5V Ta 40 C to 85 C Current consumption fscL 400 kHz Current consumption fscL 0 Hz VoD 5 0 V ET x interface inactive fscL 0 Hz fscL 0 Hz VDD 3 0V CLKOUT disabled CLKOE GND fscL 0 Hz VDD 2 0 V 5 gt Current consumption fscL 0 Hz VoD 5 0 V T gt x interface inactive fscL 0 Hz IDD32K fscL 0 Hz VDD 3 0V CLKOUT 32 kHz output LOAD is 0 pF fscL 0 Hz VoD 2 0 V L output current et VoL 0 4 V VDD 5 V output curre SD
57. ternal crystal oscillator has begun to oscillate This wait time should be about one second For details refer to the regulation for the oscillation start time tsTA s Be sure to initialize all registers Initialization For further description of initialization see Initialization below To next process Page 29 ETM12E 01 RX 8564 LC EPSON TOY M 3 Example of processing to recover from backup mode Backup recoverv processing 1 No VL 1 2 x1 Check the VL bit Voltage Low Flag x2 When the VL bit 1 it may be due to Yes 3 an error during backup clock data or VL 0 register settings may have been lost Initialization due to a voltage drop etc so be sure to initialize x3 Be sure to initialize all registers For C To next process D further description of initialization see Initialization below 4 Example of clock and calendar write processing Set current time e Write 1 to the STOP bit to prevent clock updates while setting the current STOP 1 time l l e Write the data among the Year Month Day day of Write current time week hour minute second data that needs to be set or reset When initializing be sure to initialize all of the data e Zero clear the STOP bit to start restart the clock s operation STOP 0 x The clock starts from the set second 500 ms 500 ms after the set second The
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