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RL78/G1D Datasheet - Digi-Key

1. Reference 224 for Transmission at Peak Current 10 1dBm 9 dBm 8 7 a 6 E a a 4 3 SS 2 1 0 16 18 2 22 24 28 28 3 32 94 35 38 Voltage V R01DS0258EJ0100 Rev 1 00 Page 67 of 74 Apr 24 2015 RENESAS E RL78 G1D 2 ELECTRICAL SPECIFICATIONS ian Typical Characteristic of Transmission Power RU8 G1D during RF Transmission at Peak Current 10 9 8 7 26 Es 8 2 1 0 20 18 16 4 12 10 8 8 4 2 9 2 TX POWER dBm 2 Peak Current during RF Reception Unless specified otherwise the measurement is performed by our evaluation board Current consumption is not including MCU unit TN Typical Temperature Characteristics ofthe 7 220000 Peak Current during RF Reception DCDC off 10 9 8 a 6 eee CE 8 2 1 0 50 30 10 10 30 50 70 90 Temperature C RO1DS0258EJ0100 Rev 1 00 Page 68 of 74 Apr 24 2015 RENESAS a RL78 G1D 2 ELECTRICAL SPECIFICATIONS 4 Typical Characteristics of Voltage for RU8 GiD RF Reception at Peak Current 10 9 8 7 a 6 E 8 4 Me c 3 2 1 0 16 18 2 22 24 28 28 32 34 86 38 Voltage V 3 RF Output Power during Transmission Unless specified otherwise the measurement is performed by our evaluation board
2. 1 8 V lt Voo lt 3 8 V 610 610 ns 1 6 V lt Vb lt 2 0 V 100 pF 5 5 Note Caution and Remarks are listed on the next page R01DS0258EJ0100 Rev 1 00 Page 51 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 11 Communication at different potential 1 8 V 2 5 V simplified mode 2 2 Ta 40 to 85 C 1 8 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed main Mode LS low speed main Mode LV low voltage main Mode MIN MAX MIN MAX MIN MAX Data setup time tsu DAT 2 7V lt lt 3 6 V 1 1 fwck 1 fuck ns 1 Note 3 reception 23V zVsc27 V 135 190 190 Cp 50 pF Rb 2 7 2 7 lt lt 3 6 V 1 fuck 1 fuck l fuck ns 23V V 27 V 190446 427 2 C 100 pF Ro 2 7 2 4 V lt Voo lt 3 3 V 1 1 1 ns 1 6V lt Vb lt 2 0V 190 phe C 100 pF Re 5 5 1 8 lt lt 3 3 V 1 1 ns 1 6 V lt Vo lt 2 0 VN fM 4120 C 100 pF Rb 5 5 Data hold time tHD DAT 27V lt lt 3 6 V 0 305 ov 305 305 ns transmission 23V cV x27V 50 pF Rb 2 7 27 lt lt 3 6 V go 355 gum 355 ont 355 ns 2 3 lt lt 2 7 V C 100 pF Re 2 7 2 4 V lt 3 3
3. 2 When high speed on chip oscillator and high speed system clock are stopped 3 Current flowing only to the real time clock RTC excluding the operating current of the XT1 oscillator The value of the current value of the RL78 microcontroller is the sum of the values of either Ipp1 or 052 and when the real time clock operates in operation mode or HALT mode Also add the value of IFIL in case of selecting low speed on chip oscillator 1502 subsystem clock operation includes the operational current of the real time clock 4 Current flowing only to the 12 bit interval timer including the operating current of the low speed on chip oscillator The current value of the MCU is the sum of 1 1 002 and when fsue when the watchdog timer operates in STOP mode When using low speed on chip oscillator add 5 Current flowing only to the watchdog timer including the operating current of the low speed on chip oscillator The current value of the MCU is the sum of Ipp1 002 Ipps and when the watchdog timer is in operation 6 Current flowing only to the A D converter The current value of MCU is the sum of Ipp 002 and lanc when the A D converter operates in an operation mode or the HALT mode 7 Current flowing only to the LVD circuit The current value of MCU is the sum of Ipp Ipp2 or Ipps and when the LVD circuit is in operation 8 Current flowing when operates rewriting to Da
4. Package type NB HWQFN 0 40 mm pitch ROM number Omitted with blank products Fields of application A Consumer applications operating ambient temperature Ta 40 to 85 C D Industrial applications operating ambient temperature Ta 40 to 85 C ROM capacity G 128KB H 192KB J 256 Pin count 48 pin RL78 G1D group Memory type F Flash memory Renesas MCU Renesas semiconductor product Table 1 1 List of Ordering Part Numbers Note Pin count Package Fields of Application Plastic WQFN 6 x 6 R5F11AGGANB 20 R5F11AGGANB 40 R5F11AGGDNB 20 R5F11AGGDNB 40 5 11 20 5 11 40 5 11 20 5 11 40 R5F11AGJANB 20 R5F11AGJANB 40 R5F11AGJDNB 20 R5F11AGJDNB 40 Ordering Part Number Code Flash Memory Data Flash Memory Note For the fields of application see Figure 1 1 Part Number Memory Size and Package of RL78 G1D Caution The ordering part numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website RO1DS0258EJ0100 Rev 1 00 Page 4 of 74 RENESAS m RL78 G1D CHAPTER 1 OUTLINE 1 3 Pin Configuration Top View e 48 pin plastic WQFN 6 x 6 mm 0 4 mm pitch I XTAL2 RF AVss RF r DCLOUT I XTAL1 RF I GPIOO TX
5. R01DS0258EJ0100 Rev 1 00 Page 58 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 When reference voltage AVnErFP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 conversion target ANI16 to ANI19 Ta 40 to 85 1 6 V x AVrerp lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Reference voltage AVrerp Reference voltage AVrerm 0 V Parameter Conditions Resolution Overall error 10 bit resolution 1 8 V x lt 3 6 V Note 3 AVrer 1 6 V lt AVnere lt 3 6 Conversion time 10 bit resolution 27 lt 0 lt 3 6 V 39 1 8 V lt Voo lt 3 6 V 39 1 6 lt AVrere lt 3 6 V 95 Zero scale error 10 bit resolution 1 8 V x lt 3 6 V 0 35 AVnere Voo 1 6 V lt AVrere lt 3 6 0 60 Full scale error 10 bit resolution 1 8 V lt AVnere lt 3 6 V 0 35 1 6 V lt AVnere lt 3 6 V 0 60 Integral linearity error 10 bit resolution 1 8 V lt AVnere lt 3 6 V 3 5 Note 3 AVrer 1 6 V x AVnere lt 3 6 V4 16 0 Differential linearity error 10 bit resolution 1 8 V lt AVnere lt 3 6 V 2 0 Note 3 AVnre 1 6 V lt AVnere lt 3 6 V n 2 5 Analog input voltage Notes 1 Excludes quantization error 1
6. 00000000000 4B Reference Dimensions in millimeters a Symbol Min Nom Max D2 5 D 5 90 6 00 6 10 A C 1 5 90 6 00 6 10 E 0 80 Pe 9 Ai 0 00 b 0 15 0 20 025 C 0 40 l Lp 0 20 0 30 0 40 600000000000 x 0 05 36 25 Zp 0 05 Lb DT Zo 080 ZE 0 80 0 20 D2 E 4 73 2 4 73 2015 Renesas Electronics Corporation All rights reserved R01DS0258EJ0100 Rev 1 00 Page 74 of 74 Apr 24 2015 RENESAS Revision History RL78 G1D Data Sheet Description Date Summary Apr 24 2015 First Edition issued trademarks and registered trademarks are the property of their respective owners SuperFlash is a registered trademark of Silicon Storage Technology Inc in several countries including the United States and Japan Caution This product uses SuperFlash technology licensed from Silicon Storage Technology Inc NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between VIL MAX and VIH MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between VIL MAX
7. 1 1 fuck 430 430 30 1 8 V lt Voo lt 3 6 V 1 1 30 30 1 6 V lt Voo lt 3 6 1 40 hold time 2 4 V lt Voo lt 8 6 V 1 1 1 5 7 31 31 31 1 8 V lt lt 3 6 V 1 1 fuck 31 31 1 6 V lt Voo lt 3 6 V 1 fuck 250 Delay time from C 30pF 2 7 lt lt 3 6 2 2 fmck 2 fmck SCKp to SOp io 110 me Note 2 24V lt x 3 6 V 2 2 2 output 75 110 110 1 8 V lt Voo lt 3 6 V 2 2 110 110 1 6 V lt Voo lt 3 6 V 2 220 Notes 1 When DAPmn 0 and CKPmn 0 DAPmn 1 and CKPmn 1 time becomes to when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpf when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 Cisthe load capacitance of the SOp output lines 4 Transfer rate in the SNOOZE mode MAX 1 Mbps Caution and Remarks are listed on the next page R01DS0258EJ0100 Rev 1 00 Page 34 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS Caution Select the normal input buffer for the Slp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g PIMg and port output mode
8. RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS CSI mode connection diagram during communication at different potential Master SO Users device microcontroller Remarks 1 Re O Communication line SCKp SOp pull up resistance Ce F Communication line SCKp SOp load capacitance Ve V Communication line voltage 2 p CSI number 00 m Unit number m 0 n Channel number 0 9 PIM and POM number g 1 3 Operation clock frequency of the serial array unit Operation clock to be set by the CKSmn bit of the serial mode register mn SMRmn m Unit number n Channel number mn 00 R01DS0258EJ0100 Rev 1 00 Page 45 of 74 Apr 24 2015 ztENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and 0 or DAPmn 1 and CKPmn 1 tkcvi tn SCKp SOp Output data CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcvi SCKp SOp Output data Caution Select the TTL input buffer for the pin and the N ch open drain output tolerance mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg Remark CSI number 00
9. Ta 40 to 85 C 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Conditions Output 2 0 mA POO 01 P02 P10 2 7 V lt Voo lt 3 6 V Voo 0 6 voltage lou 1 5 mA P11 P12 PIS P14 P15 1 lt lt 3 6 0 5 high P16 P30 P40 P120 P140 1 0 mA P147 1 6 V lt Voo lt 3 6 V Voo 0 5 10 pA 130 Voo 0 3 100 pA P20 P21 P22 P23 Voo 0 5 2 0 mA GPIOO GPIO1 GPIO2 2 7 V lt lt 3 6 V Vpp nr 0 3 lou 1 5 mA GPIO3 1 8 lt Voo lt 3 6 V Vop nr 0 3 Output lo 3 0 mA POO P01 P02 P10 2 7 V lt lt 3 6 V voltage low lo 1 5 mA P11 P12 P13 P14 P15 P16 P30 P40 P120 P130 lo 0 6 mA P140 P147 1 8 V lt Voo x 3 6 V lo 0 3 mA 1 66 V lt Voo lt 3 6 V lo 400 uA P20 P21 P22 P23 GPIOO GPIO1 GPIO2 GPIO3 lt lt lt lt lt lt lt lt lt lt Caution P02 P03 and P10 to P15 do not output high level in N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins R01DS0258EJ0100 Rev 1 00 Page 17 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 4 4 Input leakage current Ta 40 to 85 C 1 6 V lt Voo
10. 1 6 V lt Voo lt 3 6 V 4 7 LS Hold time when SCLAO 2 7 V lt Voo lt 3 6 V 4 0 4 0 4 0 HS Lu 24V lt Voo x 8 6 V 4 0 4 0 4 0 n 1 8 V lt Voo lt 3 6 V 4 0 4 0 Lus 1 6 V lt Voo lt 3 6 V 4 0 LS Data setup time tsu DAT 2 7 V lt Voo x 3 6V 250 250 250 ns reception 24V lt Voo lt 3 6 V 250 250 250 ns 1 8 V lt Voo lt 3 6 V 250 250 ns 1 6 V lt Voo lt 3 6 V 250 ns Data hold time tHD DAT 2 7 V lt Voo lt 3 6 V 0 3 45 0 3 45 0 3 45 us transmission 24V Vo 36V 345 345 345 us 1 8 V lt Voo lt 3 6 V 0 3 45 0 3 45 us 1 6 V lt Voo lt 3 6 V 0 3 45 us Setup time of stop tsu sro 2 7 V lt Voo x 3 6V 4 0 4 0 4 0 8 condition 24V lt V x 3 6 V 4 0 4 0 4 0 us 1 8 V lt Voo lt 3 6 V 4 0 4 0 Lus 1 6 V lt Voo lt 3 6 V 4 0 LS Bus free time teur 2 7 V lt Voo lt 3 6 V 4 7 4 7 4 7 8 2 4 V lt Voo lt 3 6 V 4 7 4 7 4 7 Lus 1 8 V lt Voo lt 3 6 V 4 7 4 7 8 1 6 V lt lt 3 6 V 4 7 LS Notes Caution and Remark are listed on the next page RO1DS0258EJ0100 Rev 1 00 Page 54 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution The values in th
11. 32 bits 32 bits 32 bits Unsigned Multiply accumulate 16 bits x 16 bits 32 bits 32 bits Unsigned or signed DMA controller 4 channels Vectored interrupt Internal 29 Aue 3 Reset e Reset by RESET pin e Internal reset by watchdog timer e Internal reset by power on reset e Internal reset by voltage detector e Internal reset by illegal instruction execution Internal reset by RAM parity error Internal reset by illegal memory access Note 4 Power on reset circuit Power on reset 1 51 TYP e Power down reset 1 50 TYP Voltage detector e Rising edge 1 67 V to 3 13 V 12 stages e Falling edge 1 63 V to 3 06 V 12 stages On chip debug function Provided Power supply voltage range 1 6 to 3 6 V Voo 1 8 to 3 6 V on usage of DC DC converter Operating ambient temperature 40 to 85 Notes 1 The number of outputs varies depending on the setting of channels in use and the number of the master 48 pin QFN 6 x 6 0 4 mm pitch 2 When setting to PIORO 1 3 When RF is used this count includes the pins that connect the MCU with the RF transceiver by the user externally on the board 4 The illegal instruction is generated when instruction code is executed Reset by the illegal instruction execution not issued by emulation with the on chip debug emulator R01DS0258
12. Current consumption is not including MCU unit For Typical Temperature Characteristics of the 178 610 Output Power during RF Transmission 3 2 0 2 E 3 Y C 50 30 10 10 30 50 70 Temperature 1 R01DS0258EJ0100 Rev 1 00 Page 69 of 74 Apr 24 2015 134 NE SAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS 4 Typical Characteristics of Voltage for Output Power during RF Transmission 3 2 3 0 0 amp 4 18 18 2 22 24 28 28 3 32 34 35 38 Voltage V For Reference Typical Frequency Characteristic for Output 78 610 Power RF Transmission 3 2 UM TX POWER dBm e 3 2400 2410 2420 2430 2440 2450 2460 2470 2480 Frequency MHz R01DS0258EJ0100 Rev 1 00 Page 70 of 74 Apr 24 2015 ztENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS 4 RF Reception Sensitivity Unless specified otherwise the measurement is performed by our evaluation board Current consumption is not including MCU unit x Typical Characteristic for Sensitivity vs Temperature RF Reception 86 88 5 82 a 9 5 96 5 98 10 50 30 10 10 30 50 70 90 Temperature 5 Typical Characteristic for Se
13. SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 6503 0 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd Room 1709 Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100191 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 301 Tower A Central Towers 555 Langao Road Putuo District Shanghai P R China 200333 Tel 86 21 2226 0888 Fax 86 21 2226 0999 Renesas Electronics Hong Kong Limited Unit 1601 1611 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2886 9022 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei 10543 Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 80 Bendemeer Road Unit 06 02 Hyflux Innovation Centre Singapore 339949 Tel 65 6213 0200 Fax 65 6213 0300 Renesas Electronics Malaysia Sdn Bhd Unit 1207 Block B Menara Amcorp Amcorp Trade Centre No 18 Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics India Pvt Ltd No 777C 100 Feet Road HALII Stage Indiranagar Bangalore India Tel 91 80 67208700 Fax 91 80 67208777 Renesas Electronics Korea Co Ltd 12F 234 Teheran ro Gangnam Gu Seou
14. load capacitance 2 p CSI number 00 20 m Unit number n Channel number 00 10 g PIM and POM number g 0 1 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 10 R01DS0258EJ0100 Rev 1 00 Apr 24 2015 Page 49 of 74 ztENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and 0 or DAPmn 1 and CKPmn 1 tkcv2 2 tku2 SCKp SOp Output data CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcv2 tku2 tkL2 SCKp SOp Output data Caution Select the TTL input buffer for the pin and the N ch open drain output Voo tolerance mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g Remark CSI number 00 m Unit number 0 n Channel number 0 9 and POM number 9 1 R01DS0258EJ0100 Rev 1 00 Page 50 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 11 Communication at different potential 1 8 V 2 5 V simplified mode 1 2 Ta 40 to 85 C 1 8 V lt Voo Vo
15. m Unit number 0 n Channel number 0 9 POM number g 1 RO1DS0258EJ0100 Rev 1 00 Page 46 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 10 Communication at different potential 1 8 V 2 5 V CSI mode slave mode SCKp external clock input 1 2 Ta 40 to 85 C 1 8 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MAX SCKp cycle time 2 7 lt Voo lt 3 6 V 24 MHz lt fuck 20 2 3 lt lt 2 7 V fuck 20 MHz lt fuck x 24 MHz 16 16 MHz lt fmck lt 20 MHz 14 8 MHz lt fuck lt 16 MHz 12 fuck 4 MHz lt fuck lt 8 MHz 8 fuck fuck lt 4MHz 6 fuck 2 4 V lt Voo lt 3 3 V 24 MHz lt fuck 48 1 6 V lt lt 2 0 20 MHz lt fuck x 24 MHz 36 16 MHz lt fuck lt 20 MHz 32 8 MHz lt lt 16 MHz 26 fuck 4 MHz lt fuck lt 8 MHz 16 fuck fuck lt 2 10 fuck 1 8 V Voo lt 3 3 24 MHz lt E 1 6V lt Ve lt 2 0V 20 MHz lt fuck lt 24 MHz 16 MHz lt fuck lt 20 MHz 8 MHz lt fuck lt 16 MHz 4 MHz lt fuck lt 8 MHz fuck lt 4MHz Note Caution and Remarks are listed on t
16. nr lt 3 6 V Vss Vss nr AVss nr 0 V Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MAX MAX MAX Reception 2 7VxVbopx 3 6 V 2 3 V lt Vo lt 2 7 V fuck 6 0491 fuck 6 91 6 Theoretical value of the maximum 5 3 1 3 0 6 transfer rate Note 3 fork lt 0 lt 3 3 V 1 6 V lt x 2 0 V fmck 6 91 fuck 6 fuck 6 91 Theoretical value of the maximum 2 6 1 3 0 6 transfer rate Note 3 fork lt 3 3 V 1 6 V lt Vb lt 2 0 V fuck 6 o fuck 6 6981 2 Theoretical value of the maximum 1 3 1 3 transfer rate Note 3 fork Transmission 2 lt lt 3 6 V 2 3 V lt lt 2 7 V Note 4 Theoretical value of the maximum 1 2 Nore transfer rate Co 50pF Ro 2 7 Vb 2 3 V lt lt 3 8 V 1 6 V x Vo x 2 0 V Notes 2 6 Notes 2 6 Notes 2 6 Theoretical value of the maximum 0 43 0 43 0 43 transfer rate Cp 50pF Ro 5 5 Vo 1 6 V lt lt 3 3 V 1 6 V Vo x 2 0 V Notes 2 6 Notes 2 6 Theoretical value of the maximum 0 43 7 0 43 7 transfer rate Cb 50 pF Ro 5 5 Vo 1 6 V Transfer rate in the SNOOZE mode is 4800 bps only Use it with gt Vb Maximum operating frequency of CPU and peripheral hardware clock is following HS high speed main mode 32 MHz 2 7 V lt Von lt 3 6 V 16 MHz
17. 0 V Reference voltage Resolution Parameter Conditions Note 3 Reference voltage AVneru 0 V HS high speed main mode Conversion time 8 bit resolution 2 4 V lt Voo lt 3 6 V 39 Zero scale error Notes 1 2 8 bit resolution 2 4 V lt Voo lt 3 6 V 10 60 Integral linearity error 8 bit resolution 2 4 V lt Voo lt 3 6V 2 0 9 Differential linearity error 8 bit resolution 2 4 V lt Voo lt 3 6 V 1 0 Analog input voltage Veer Note 3 Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 Refer to 2 8 2 Temperature sensor and internal reference voltage characteristics 4 When reference voltage Vss MAX value is following Zero scale error 0 35 FSR is added to the MAX value of reference voltage Integral linearity error 30 5 LSB is added to the MAX value of reference voltage AVREFM Differential linearity error 0 2 LSB is added to the MAX value of reference voltage AVREFM R01DS0258EJ0100 Rev 1 00 Page 61 of 74 Apr 24 2015 ztENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 8 2 Temperature sensor and internal reference voltage characteristics Ta 40 to 85 C 2 4 V lt nr nr lt 3 6 V Vss Vss nr AVss nr 0 V HS high speed main mode Parameter Conditions Temperature se
18. 1 8 V x AVnere lt 3 6 V 0 25 493 1 6 V lt AVnere lt 3 6 V 0 50 Full scale error 10 bit resolution 1 8 V lt AVnere lt 3 6 V 0 25 AVrerp 1 6 V x AVnere lt 3 6 V 0 50 Integral linearity error 10 bit resolution 1 8 V lt AVnere lt 3 6 V 2 5 Note 3 AVrerp 1 6 V lt AVnere lt 3 6 V 5 0 Differential linearity error 10 bit resolution 1 8 V lt AVnere lt 3 6 V 1 5 Note 1 Note 3 1 6 V lt AVnere lt 3 6 V 2 0 Analog input voltage ANI12 ANI13 AVREFP Note 5 Select internal reference voltage 2 4 V lt Vop lt 3 6 V HS high speed mode Note 5 Select temperature sensor output voltage VTMPS25 2 4 V Vop 3 6 V HS high speed main mode Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 When AVnerP lt MAX value is following Overall error 1 LSB is added to the MAX value of AVnerP VoD Zero scale error Full scale error 0 05 FSR is added to the MAX value of Integral linearity error Differential linearity error 0 5 LSB is added to the MAX value of AVnere VoD 4 When the the conversion time is set to 57 us min and 95 us max 5 Referto 2 8 2 Temperature sensor and internal reference voltage characteristics
19. 2 4 V lt Vo0 lt 3 6V tkcvi 2 tkcvi 2 tkcvi 2 38 50 50 18 lt lt 3 6 tkcvi 2 tkcvi 2 50 50 1 6 lt lt 3 6 tkcvi 2 100 51 setup time 2 7 V lt Voo lt 3 6 V 110 to SCKpT 24 V lt Voo lt 3 6 V 110 1 8 V lt Voo lt 3 6 V 1 6 V lt Voo lt 3 6 V 220 ns 51 hold time tksi1 2 7 V lt Voo lt 3 6 V 19 19 19 ns from SCKpt 24V lt lt 3 6 V 19 19 19 ns 1 8 V lt Voo lt 3 6 V 19 19 ns 1 6 V lt Voo lt 3 6 V 19 ns Delay time from tkso C 30pF 2 7 lt lt 3 6 25 25 25 ns to SOp 2 4 V lt Voo lt 3 6 V 25 25 25 ns output 992 1 8 V lt lt 3 6 V 25 25 ns 1 6 V lt Voo lt 3 6 V 25 ns Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 time becomes to when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpf when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 is the load capacitance of the SCKp and 50 output lines Caution Select the normal input buffer for the and the normal output mode for the SOp pin and SCKp by using port input mode register g PIMg and port output mode register g POMg Remarks 1 CSI number 00 10 m
20. 33 110 110 ns to SCKpJ 23V lt Vb 27 V Co 20 pF Rb 2 7 Slp hold time tksit 2 7 V lt Voo lt 3 6 V 10 10 10 ns from 23VxVs 27 V C 20 pF Rb 2 7 Delay time from tkso1 2 7 V lt Voo lt 3 6 V 10 10 10 ns SCKpf to SOp output Note 2 2 3 V lt lt 2 7 V Co 20 pF Rb 2 7 Notes 1 When DAPmn 0 and CKPmn 0 DAPmn 1 and CKPmn 1 2 When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Caution Select the TTL input buffer for the pin and the N ch open drain output Voo tolerance mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and see the DC characteristics with TTL input buffer selected Remarks 1 Rb Q Communication line SCKp SOp pull up resistance Ce F Communication line SCKp SOp load capacitance Ve V Communication line voltage 2 p CSI number p 00 m Unit number m 0 n Channel number 0 9 PIM and POM number g 1 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 R01DS0258EJ0100 Rev 1 00 Apr 24 2015 134 NE SAS Page 42 of 74 RL78 G1D 2 ELECTRICAL SPECIFICATIONS 9 Communication at different potential 1 8 V 2 5 V CSI mode master mode SCKp i
21. 5 51 setup time 2 7 V lt Voo lt 3 6 V to 2 3V lt Vo lt 2 7V Co 30 pF Re 2 7 2 4 V lt lt 3 3 1 6 lt lt 2 0 Cb 30 pF Rb 5 5 1 8 V lt lt 3 3 V 1 6 V lt Vb lt 2 0 V C 30 pF Rb 5 5 hold time 27V lt Vo lt 3 6 V Note 2 from 23V V x27 V Cb 30 pF Rb 2 7 2 4 V lt lt 3 3 1 6V lt Vo lt 2 0V C 30 pF 5 5 1 8 V lt lt 3 3 V 1 6 V lt Vb lt 2 0 V C 30 pF Rb 5 5 Delay time from SCKpt 2 7 lt lt 3 6 V Note 2 to SOp output 2 3V lt Vo lt 2 7V C 30 pF Rb 2 7 2 4 V lt lt 3 3 1 6 lt lt 2 0 V Cb 30 pF Ro 5 5 1 8 lt lt 3 3 V 1 6 V lt Vb lt 2 0 V 30 pF 5 5 KQ Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 2 When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 Use it with gt Vb Caution Select the TTL input buffer for the pin and the N ch open drain output Voo tolerance mode for the SOp pin and SCKp by using port input mode register PIMg and port output mode register 0 POMg For and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the next page R01DS0258EJ0100 Rev 1 00 Page 44 of 74
22. 6 to 1 8 V High speed on chip oscillation clock HS High speed main mode 1 to 32 MHz 2 7 to 3 6 V HS High speed main mode 1 to 16 MHz 2 4 to 3 6 V LS Low speed main mode 1 to 8 MHz Voo 1 8 to 3 6 V LV Low voltage main mode 1 to 4 MHz 1 6 to 3 6 V Subsystem clock Crystal oscillation External main system clock input EXCLKS 32 768 kHz TYP RF slow clock External input External clock input for RF block EXSLK RF 32 768 kHz TYP On chip Oscillator 32 768 kHz TYP Low speed on chip oscillator 15 kHz TYP General purpose register 8 bit register x 8 x 4 banks Minimum instruction execution time 0 03125 ws High speed on chip oscillation clock 32 MHz operation 0 05 us High speed system clock fmx 20 MHz operation 30 5 us Subsystem clock fsus 32 768 kHz operation Instruction set Data transfer 8 16 bits e Adder and subtractor logical operation 8 16 bits e Multiplication 8 bits x 8 bits e Rotate barrel shift and bit manipulation Set reset test and Boolean operation etc Total Boke 2 CMOS I O 200 2 CMOS input 5 Note 2 CMOS output 1 Note 2 N ch O D I O 2 GPIO RF block 4 2 4 GHz RF transceiver Supporting Bluetooth v4 1 Specification Single mode 2 4 GHz ISM Band GFSK modulation TDMA TDD frequency hopping
23. Points Test points a TS External System Clock Timing 1 fex 1 fexs EXCLK EXCLKS TI TO Timing tri TIOO to TIO7 TI10 to TI17 1 fro TOO0 to TO10 to TO17 Interrupt Request Input Timing INTPO INTPS INTP5 INTP6 RESET Input Timing trsL RESET RO1DS0258EJ0100 Rev 1 00 Page 28 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 7 Peripheral Functions Characteristics AC Timing Test Points Test point Vi VoL Ne M 2 7 1 Serial array unit 1 During communication at same potential UART mode Ta 40 to 85 C 1 6 V lt Voo Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MAX MAX MAX Transfer rate 99 2 4 V lt Voo lt 3 6 V Theoretical value of the maximum transfer rate Note 2 fork 1 8 V lt Voo lt 3 6 V Theoretical value the maximum transfer rate Note 2 fork 1 6 V lt Vio lt 3 6 V Theoretical value of the maximum transfer rate Note 2 fou Notes 1 Transfer rate in the SNOOZE mode is 4800 bps only 2 Maximum operating frequency of CPU and peripheral hardware clock is following HS high speed main
24. Start Restart Stop condition condition condition condition Remark n 0 RO1DS0258EJ0100 Rev 1 00 Page 57 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 8 Analog Characteristics 2 8 1 A D converter characteristics A D convertor characteristics category Reference voltage Ref voltage AVnere Ref voltage Voo Ref voltage Ref voltage AVrerm Ref voltage Vss Ref voltage AVrerm ANIO Refer to 2 8 1 3 Refer to 2 8 1 4 ANI1 ANI2 Refer to 2 8 1 1 Refer to 2 8 1 4 ANI16 to ANI19 Refer to 2 8 1 2 Internal reference voltage Refer to 2 8 1 1 Temperature sensor output voltage 1 When reference voltage AVnErP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 conversion target ANI2 Internal reference voltage Temperature sensor output voltage Ta 40 to 85 1 6 V lt lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Reference voltage Reference voltage AVrerm 0 V Parameter Conditions Resolution Overall error 10 bit resolution 1 8 V x AVnere lt 3 6 V Note 3 1 6 V lt AVnere lt 3 6 V4 Conversion time 10 bit resolution 2 7 V lt lt 3 6 V 39 1 8 x AVnere lt 3 6 V 39 1 6 V x AVnere lt 3 6 V 95 Zero scale error 10 bit resolution
25. Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 2 4 2 Input current Ta 40 to 85 C 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Conditions Input voltage high POO P01 PO2 POS P10 P11 Normal mode Im 1 P12 P13 P14 P15 P16 P30 P40 P120 P130 P140 P147 P01 P10 P11 P13 P14 TTL mode 2 0 P15 P16 3 3 V lt Voo lt 3 6 V TTL mode 1 5 1 6 V lt Voo lt 3 3V P20 P21 P22 P23 0 7 5 P60 P61 0 7Vpp P121 P122 P123 P124 P137 RESET 0 8Vpp GPIOO GPIO1 GPIO2 GPIO3 0 85Vpp Input voltage low POO P01 PO2 POS P10 P11 Normal mode ItH 1 0 P12 P13 P14 P15 P16 P30 P40 P120 P140 P147 P01 P10 P11 P13 P14 TTL mode 0 5 P15 P16 3 3 V lt Voo lt 3 6 V TTL mode 0 32 1 6 lt Voo lt 3 3V P20 P21 P22 P23 0 3Vpp P60 P61 0 3Vpp P121 P122 P123 P124 P137 RESET 0 2Vpp GPIOO GPIO1 GPIO2 GPIO3 0 1Vpp_RF Caution The maximum value of of pins P00 P02 and P10 to P15 is Voo even in the N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0258EJ0100 Rev 1 00 Page 16 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 4 3 Output voltage
26. distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 24 NE SAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2801 Scott Boulevard Santa Clara CA 95050 2549 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 9251 Yonge Street Suite 8309 Richmond Hill Ontario Canada L4C 9T3 Tel 1 905 237 2004 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire
27. for use in operation as a slave device Code flash memory e Code flash memory 128 to 256 KB e Block size 1 e Prohibition of block erase and rewriting security function e On chip debug function e Self programming with boot swap function flash shield window function Data flash memory e Data flash memory 8 KB e Back ground operation BGO Instructions can be executed from the program memory while rewriting the data flash memory e Number of rewrites 1 000 000 times TYP Voltage of rewrites Voo 1 8 to 3 6 V R01DS0258EJ0100 Rev 1 00 Page 1 of 74 RENESAS a RL78 G1D CHAPTER 1 OUTLINE High speed on chip oscillator e Select from 32 MHz TYP 24 MHz TYP 16 MHz TYP 12 MHz TYP 8 MHz TYP 6 MHz TYP 4 MHz TYP 3 MHz TYP 2 MHz TYP and 1 MHz TYP Low speed on chip oscillator e 15 kHz TYP On chip oscillator for the RF slow clock 32 768 kHz Operating ambient temperature 40 to 85 C A Consumer applications D Industrial applications Power management and reset function e On chip power on reset POR circuit e On chip voltage detector LVD Select interrupt and reset from 12 levels DMA Direct Memory Access controller e 4channels e Number of clocks during transfer between 8 16 bit SFR and internal RAM 2 clocks Multiplier and divider multiply accumulator e 16 bits x 16 bits 32 bits Unsigned or signed e 32 bits 32 bits 32 bits Unsig
28. mode 32 MHz 2 7 V lt Voo x 3 6 V 16 MHz 2 4 V lt Voo lt 3 6 V LS low speed mode 8 MHz 1 8 V lt Voo 3 6 V LV low voltage main mode 4 1 6 V x lt 3 6 V Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg R01DS0258EJ0100 Rev 1 00 Page 29 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS UART mode connection diagram during communication at same potential TxDq RL78 microcontroller User device RxDq UART mode bit width during communication at same potential reference 1 Transfer rate High Low bit width Baud rate error tolerance TxDq RxDq Remarks 1 UART number 0 1 9 PIM and POM number g 0 1 2 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 01 R01DS0258EJ0100 Rev 1 00 Page 30 of 74 Apr 24 2015 RENESAS RL78 G1D 2 During communication at same potential CSI mode master mode SCKp internal clock output supporting CSI00 only 2 ELECTRICAL SPECIFICATIONS Ta 40 to 85 C 2 7 V lt Voo nr rr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter SCKp cycle time tkcy1 gt 2 fcik Conditions HS high speed ma
29. nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Conditions Input leakage current POO P01 P02 P10 P11 P12 P13 P14 high P15 P16 P30 P40 P60 P61 P120 P140 P147 P20 P21 P22 P23 P137 RESET P121 P122 P123 In input port P124 EXCLK EXCLKS XT1 XT2 In external clock input In resonator connection GPIOO GPIO1 GPIO2 GPIO3 Input leakage current POO P01 P02 P10 P11 P12 P13 P14 low P15 P16 P30 P40 P60 P61 P120 P140 P147 P20 P21 P22 P23 P137 RESET P121 P122 P123 In input port P124 EXCLK EXCLKS XT1 XT2 In external clock input In resonator connection VI Vss GPIOO GPIO1 GPIO2 GPIO3 Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 2 4 5 Resistance Ta 40 to 85 C 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Conditions On chip pll up POO 01 02 P10 P11 P12 P13 P14 resistance P15 P16 P30 P40 P120 P140 P147 In input mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0258EJ0100 Rev 1 00 Page 18 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 5 Current Drawn The current drawn by the RL78 G1D is the total cu
30. transferred bits 7 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer Caution Select the TTL input buffer for the RxDq pin and the N ch open drain output tolerance mode for the TxDq by using port input mode register PIMg and port output mode register POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks 1 Re O Communication line TxDq pull up resistance Communication line TxDq load capacitance Ve V Communication line voltage 2 q UART number 0 1 9 and POM numbers g 0 1 3 Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 UART mode connection diagram during communication at different potential Vb E User device RL78 microcontroller RxDq UART mode bit width during communication at different potential reference 1 Transfer rate Low bit width High bit width Baud rate error tolerance Da ores 3 TxDq 1 Transfer rate High Low bit width Baud rate error tolerance RxDq Remarks 1 Re O Communication line TxDq pull up resistance Ve V Communication li
31. 2 4 V lt lt 3 6 V LS low speed main mode 8 MHz 1 8 V lt lt 3 6 V LV low voltage main mode 4 MHz 1 8 V lt Voo lt 3 6 V The smaller maximum transfer rate derived by using 6 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 2 7 V lt 3 6 V and 2 3 V lt Vb x 2 7 V Maximum transfer rate 1 Cb x Rb x In 1 2 0 Vb x 3 bps Baud rate error theoretical value 1 transfer rate x 2 Cb x Rb In 1 2 0 Vb 1 transfer rate x number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer The smaller maximum transfer rate derived by using 6 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 1 8V lt lt 3 3 V and 1 6 V lt Vb lt 2 0 V Maximum transfer rate 1 Cb x Rb x In 1 1 5 Vb x 3 bps R01DS0258EJ0100 Rev 1 00 Page 40 of 74 Apr 24 20 RENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS Baud rate error theoretical value 1 transfer rate x 2 Cb x Rb x In 1 1 5 Vb 1 transfer rate x number of
32. 2 LSB 2 This value is indicated as a ratio YFSR to the full scale value 3 When lt MAX value is following Overall error 4 LSB is added to the MAX value of VoD Zero scale error Full scale error 0 2 FSR is added to the MAX value of AVrerr Integral linearity error Differential linearity error 2 LSB is added to the MAX value n of AVnere 4 When the the conversion time is set to 57 us min and 95 us max R01DS0258EJ0100 Rev 1 00 Page 59 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 3 When reference voltage ADREFP1 0 ADREFPO 0 reference voltage Vss ADREFM 0 conversion target ANIO to ANI3 ANI16 to ANI19 Internal reference voltage Temperature sensor output voltage Ta 40 to 85 C 1 8 V lt Voo Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Reference voltage Reference voltage Vss Parameter Conditions Resolution 10 bit resolution 1 8 V lt Voo lt 3 6 V 1 6 V lt lt 3 6 V Overall error Conversion time 10 bit resolution 2 7 V lt lt 3 6 V conversion 1 8 V lt Voo lt 3 6 V target ANIO to 7 lt ANI 18 Ve lt 3 6 ANI19 10 bit resolution 2 7 V lt Voo lt 3 6 V conversion target Internal reference voltage Temperature sensor output 2 7 V lt Voo lt 3 6
33. 21 P22 P23 P30 P40 P60 P61 P120 P130 P140 P147 0 3 to Vop 0 3 GPIOO GPIO1 GPIO2 GPIO3 DCLOUT 0 3 to nr4 0 3 Analog input ANIO ANI1 ANI2 ANI3 ANI16 ANI17 ANI18 ANI19 0 3 to 0 3 and voltage 0 3 to Vngr 40 3 69824 REGC pin input voltage REGC 0 3 to 2 8 and 0 3 to Vop 0 3 IC pin input ICO IC1 0 5 to 0 3 voltage Notes 1 Must be 6 5 V or lower 2 Must be 4 0 V or lower 3 Connect the REGC pin to Vss via a capacitor 0 47 to 1 pF maximum rating of the REGC pin Do not use this pin with voltage applied to it This value regulates the absolute 4 Do not exceed AVrer 0 3 V in case of A D conversion target Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remarks 1 Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 2 AVre o Side reference voltage of the A D converter 3 Reference voltage is Vss R01DS0258EJ0100 Rev 1 00 Apr 24 2015 Page 11 of 74 134 NE SAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS Absolute Maximum
34. 7 2 4 V lt Voo lt 3 3 V 2 2 1 6 lt lt 2 0 573 573 30 pF 5 5 1 8 V lt Voo lt 3 3 2 1 6 lt V x2 0V 573 30 pF 5 5 Note 2 Notes 1 Transfer rate in the SNOOZE mode 1 Mbps 2 Use it with gt Vb 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The time becomes to when DAPmn 0 and CKPmn 1 or DAPmn 1 and 0 4 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpf when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Caution Select the TTL input buffer for the and SCKp pin and the N ch open drain output tolerance mode for the SOp pin by using port input mode register g PIMg and port output mode register g POMg For and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the next page R01DS0258EJ0100 Rev 1 00 Page 48 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS CSI mode connection diagram during communication at different potential Slave SCKp RL78 microcontroller 51 Remarks 1 Re O Communication line SOp pull Ve V Communication line voltage Vb p SCK SO User device up resistance Communication line SOp
35. EJ0100 Rev 1 00 Apr 24 2015 Page 9 of 74 ztENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 ELECTRICAL SPECIFICATIONS Caution The RL78 microcontrollers have an on chip debug function which is provided for development and evaluation Do not use the on chip debug function in products designated for mass production because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug function is used R01DS0258EJ0100 Rev 1 00 Page 10 of 74 Apr 24 2015 ztENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 1 Absolute Maximum Ratings Absolute Maximum Ratings Ta 25 C 1 2 Parameter Supply voltage Symbols Voo Conditions Voo Ratings 0 5 to 46 5 1 Vpp RF 0 5 to 44 0 2 RF 0 5 to 44 0 DCLIN 0 5 to 44 0 VssnF Vss AVss RF 0 5 to 40 3 Input voltage POO P01 P02 POS P10 P11 P12 P14 P15 P16 P20 P21 P22 P23 P30 P40 P120 P121 P122 P123 P124 P137 P140 P147 RESET 0 3 to Vpp40 3 P60 P61 0 3 to 6 5 GPIOO GPIO1 GPIO2 GPIO3 0 3 to 0 3 492 ANT 0 5 to 41 4 Output voltage POO P01 P02 POS P10 P11 P12 P14 P15 P16 P20 P
36. F 2 7 2 4 V lt Voo lt 3 3 V 1 6 V Vo lt 2 0 V C 30 pF Ro 5 5 1 8 V lt lt 3 3 V 1 6 V Vo lt 2 0 V C 30 pF Rb 5 5 51 hold time 2 7 V lt Voo lt 3 6 2 3 V Vo x27 V from SCKpf Co 30 pF Re 2 7 24 V lt Voo lt 3 3 V 1 6 V Vo lt 2 0 V 30 pF Ro 5 5 1 8 V lt Voo lt 3 3 V 1 6 V lt Vo x 2 0 Cp 30 pF Ro 5 5 Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 2 When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 Use it with gt Vb Caution are listed on the next page R01DS0258EJ0100 Rev 1 00 Page 43 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 9 Communication at different potential 1 8 V 2 5 V CSI mode master mode SCKp internal clock output supporting CSIOO only 2 2 Ta 40 to 85 C 1 8 V lt Voo Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed 15 low speed main LV low voltage main Mode Mode main Mode MIN MAX MIN MAX MIN MAX Delay time from 5 2 7 lt lt 3 6 V Note 1 to SOp output 2 3 V Vs 2 7 V C 30 pF Ro 2 7 2 4 V lt lt 3 3 1 6 lt lt 2 0 Cb 30 pF Rb 5 5 1 8 V lt lt 3 3 1 6 V lt Vb lt 2 0 V 30 pF 5
37. F When 32 768 kHz input 0 08 When 16 384 kHz input 0 08 Timer input high level width low level width ttn tri 00 01 02 TIOS 04 TIO5 06 07 1 fuck 10 Timer output frequency TIOO TIO1 HS high speed 2 7 V Vm lt 3 6 V TIO2 1103 main mode 2 4 V lt Vo lt 2 7 V T104 05 106 T107 LV low voltage mai n mode LS low speed main mode Clock buzzer output frequency PCLBUZO HS high speed 2 7 V lt lt 3 6 V main mode 24VxVp 27V LV low voltage mai n mode LS low speed main mode CLKOUT RF Remark Timer array unit operation clock frequency Operation clock to be set by the CKSmn0 CKSmn1 bits of timer mode register mn TMRmn m Unit number m 0 1 n Channel number n 0 to 7 R01DS0258EJ0100 Rev 1 00 Apr 24 2015 134 NE SAS E Page 25 of 74 RL78 G1D 2 ELECTRICAL SPECIFICATIONS Ta 40 to 85 C 1 6 V lt nr nr lt 3 6 V Vss Vss nr AVss nr 0 V 2 2 Conditions Interrupt input high level width tirH INTPO INTP3 INTP5 INTP6 low level width INTL External PA control output High TXSELH_RF level width External PA control output low tPALRF TXSELL RF level width RESET low level width tn
38. Including AES encryption circuit Adaptivity exclusively for use in operation as a slave device 16 bit timer 8 channels Watchdog timer 1 channel Real time clock RTC 1 channel Notes 1 2 12 bit interval timer 1 channel This is about 19 KB when the self programming function is used When RF is used this count includes the pins that connect the MCU with the RF transceiver by the user externally on the board R01DS0258EJ0100 Rev 1 00 Apr 24 2015 Page 8 of 74 lt RL78 G1D Item R5F11AGG R5F11AGH R5F11AGJ Timer output CHAPTER 1 OUTLINE 8 channels PWM outputs 3 RTC output 1 channel 1 Hz subsystem clock fsue 32 768 kHz Clock output buzzer output 1 81 e 2 44 kHz 4 88 kHz 9 76 kHz 1 25 MHz 2 5 MHz 5 MHz 10 MHz Main system clock 20 MHz operation 256 Hz 512 Hz 1 024 kHz 2 048 kHz 4 096 kHz 8 192 kHz 16 384 kHz 32 768 kHz Subsystem clock fsus 32 768 kHz operation RF unit 8 10 bit resolution A D converter CLKOUT REF pin 16 MHz 8 MHz 4 MHz 8 channels Serial interface CSI simplified FC UART 1 channel CSl simplified 1 channel UART 1 channel CSI 1 channel dedicated for internal communications bus 1 channel Multiplier and divider multiply accumulator Multiplication 16 bits x 16 bits 32 bits Unsigned or signed Division
39. KOUT RF DCLIN DCLOUT EXCLK EXCLKS EXSLK RF GND1 GPIOO to ICO IC1 INTPO INTP3 INTP5 INTP6 to P10 to P16 P20 to P23 P30 P40 P60 P61 P120 to P124 P130 P137 P140 P147 Analog input PCLBUZO Antenna connection REGC Power supply for RF RFCTLEN analog RTC1HZ Analog reference voltage minus RESET Analog reference voltage RXDO RxD1 plus SCLAO SCKOO SCK20 SCLOO SCL20 Ground for RF analog Clock output DC DC converter inductor SDAAO SDAOO SDA20 and DCLOUT capacitor 100 120 DC DC converter output 5000 5020 External clock input TIOO to TIO7 Main system clock 00 to TOO7 External clock input TOOLO Subsystem clock External slow clock input TxD1 Package exposed die pad TXSELL RF GPIO at RF unit TXSELH RF Internal circuit Vpp External interrupt input RF Vss Port 0 Vss RF Port 1 X1 X2 Port 2 XT2 Port 3 XTAL1 RF Port 4 XTAL2 RF Port 6 Port 12 Port 13 Port 14 TOOLRxD TOOLTXD Programmable clock output buzzer output Regulator capacitance RF control enable Real time clock correction clock 1 Hz output Reset Receive data Serial clock input output Serial clock output Serial data input output Serial data input Serial data output Timer input Timer output Data input output for tool Data input output for external device Transmit data External PA LNA cont
40. PER lt 30 8 RF low power mode dBm RF input pin RF normal mode dBm RF high performance mode dBm Sensitivity of reception PER lt 30 8 RF low power mode dBm RF normal mode dBm RF high performance mode dBm Secondary radiation 30 MHz to 1 GHz dBm 100 kHz 1 GHz to 12 GHz dBm 100 kHz Common channel RFccr PER lt 30 8 Prf 67dBm dB rejection ratio Adjacent channel lt 30 8 1 MHz dB rejection ratio 67 dBm MHz dB 3 MHz dB Blocking lt 30 8 30 MHz 2000 MHz dB Prf 67 dBm 2000 MHz to 2399 MHz 2484 MHz to 3000 MHz 3000 MHz Frequency tolerance PER lt 30 8 250 250 ppm RSSI accuracy RFnssis 25 70 dBm lt Prf lt 10 dBm 4 0 4 dB R01DS0258EJ0100 Rev 1 00 Page 66 of 74 Apr 24 2015 ztENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 9 3 Performance mapping for typical RF Reference 1 Peak Current during RF Transmission Unless specified otherwise the measurement is performed by our evaluation board Current consumption is not including MCU unit Typical Temperature Characteristics ofthe 7 0080 Peak Current during RF Transmission DCDC off 10 9 8 7 a Eu 3 2 1 0 50 30 10 10 30 50 70 90 Temperature C seid Typical Characteristics of Voltage
41. REN ESAS Datasheet RL78 G1D R01DS0258EJ0100 RENESAS MCU Apr puce 1 OUTLINE The RL78 G1D is a microcomputer incorporating the RL78 CPU core and low power consumption RF transceiver supporting the Bluetooth ver 4 1 Low Energy Single mode specifications 1 1 Features Ultra low power consumption technology e MCU part Standby function HALT mode STOP mode SNOOZE mode e RF part Standby function POWER DOWN mode RESET RF mode STANDBY RF mode IDLE_RF mode DEEP SLEEP mode SLEEP RF mode e transmission RF normal mode 4 8 mA TYP 3 0 V MCU part STOP mode RF Low power mode 2 6 mA TYP 3 0 V MCU part STOP mode e RF reception RF normal mode 3 5 mA TYP 3 0 V MCU part STOP mode RF Low power mode 3 3 mA TYP 3 0 V MCU part STOP mode RF sleep POWER DOWN mode operation 0 10 TYP 3 0 V MCU part STOP mode RL78 CPU core e CISC architecture with 3 stage pipeline Minimum instruction execution time Can be changed from high speed 0 03125 ws 32 MHz operation with high speed on chip oscillator to ultra low speed 30 5 ws 32 768 kHz operation with subsystem clock Address space 1 General purpose registers 8 bit register x 8 x 4 banks e On chip RAM 12 to 20 KB On chip RF transceiver e Bluetooth v4 1 Specification Low Energy Single mode 2 4 GHz ISM band GFSK modulation TDMA TDD frequency hopping including AES encryption circuit e Adaptivity exclusively
42. RESET CONTROL X1 P121 SERIAL ARRAY MULTIPLIER amp UNIT 2ch CRC lt X2 EXCLK P122 DIVIDER HIGH SPEED ON CHIP 1 123 MULITIPLY SCK20 P 15 ACCUMULATOR OSCILLATOR SI20 P14 XT2 EXCLKS P124 SO20 P13 DIRECT MEMORY VOLTAGE SCL20 P15 ACCESS CONTROL REGULATOR REGC SDA20 P14 BCD ADJUSTMENT INTPO P137 INTERRUPT INTPS P30 CONTROL INTP5 P16 INTP6 P140 SCK21 P70 CONTROL GPIOO TXSELH_RF RFCTLEN GPIO1 TXSELL 32 768 kHz RF TRANSCEIVER RF Unit XTAL1 GPIO2 CLKOUT RF 5 e XTAL2 RF GPIOS EXSLK RF DCLIN DCLOUT ICO IC1 TOOLRxD P11 GND1 TOOLTxD P12 Vss RF AVop RF AVss RF Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR R01DS0258EJ0100 Rev 1 00 Page 7 of 74 RENESAS m RL78 G1D CHAPTER 1 OUTLINE 1 6 Outline of Functions Caution This outline describes the functions at the time when Peripheral I O redirection register PIOR is set to 00H 1 2 R5F11AGG R5F11AGH R5F11AGJ 256 KB 8KB 20 1 Code flash memory Data flash memory RAM 1 MB 32 MHz Address space System clock RF side Main system clock High speed system clock External main system clock input EXCLK 1 to 20 MHz 2 7 to 3 6 V 1 to 8 MHz Vpp 1 8 to 2 7 V 1 to 4 MHz Voo 1
43. Ratings Ta 25 C 2 2 Parameter Output current high Symbols Per pin Conditions This is applicable to all pins listed below Ratings Total of all pins 170 POO P01 P02 POS P40 P120 P130 P140 P10 P11 P12 P13 P14 P15 P16 P30 P147 Per pin This is applicable to all pins listed below Total of all pins P20 P21 P22 P23 loHMRF Per pin GPIOO GPIO1 GPIO2 GPIO3 Output current low lou Per pin This is applicable to all pins listed below Total of all pins 170mA POO P01 P02 POS P40 P120 P130 P140 P10 P11 P12 P13 P14 P15 P16 P30 P60 P61 P147 Per pin This is applicable to all pins listed below 1 Total of all pins P20 P21 P22 P23 5 Per pin GPIOO GPIO1 GPIO2 GPIO3 17 Operating ambient temperature In normal operation mode 40 to 85 In flash memory programming mode 40 to 85 Storage temperature 65 to 150 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remarks 1 Unless specified otherwise the characteristics o
44. SELH RF AVDD RF L ANT I9 GPIOT1 TXSELL RF BE 35 34 33 32 31 30 29 28 27 A Vss RF 43 DCLIN 38 sg 28 GPIO2 CLKOUT RF 939 GPIO3 EXSLK RF 940 P30 INTP3 RTC1HZ 441 P16 TIO1 TOO1 INTP5 42 P15 SCK20 SCL20 TI02 TO02 3443 V P61 SDDAO P60 SCLAO Vss REGC P121 X1 P122 X2 EXCLK P137 INTPO GND1 P14 SI20 SDA20 SCLAO TI03 TO03 44 P13 SO20 SDAAO TIO4 TO04 45 P123 XT1 P12 SO00 TxDO TOOLTxD TIOB TOO05 46 P124 XT2 EXCLKS P11 SI00 RXDO TOOLRxD SDAOO TIOG TO06 347 lt RESET P40 SCKO0 SCLOO TIO7 TOO7 4 48 P40 TOOLO mS 8 910 11 P130 PO3 ANI16 RxD1 INDEX MARK P147 ANI18 P23 ANI3 P22 ANI2 P21 ANI1 AVREFM P20 ANIO AVREFP P01 TOOO 00 100 P140 PCLBUZO INTP6 P120 ANI19 PO2 ANI17 TxD1 Cautions 1 Connect the REGC pin to Vss via a capacitor 0 47 to 1 2 Connect the metal pad GND1 on the back of the package that has the same potential as AVss nr Remarks 1 For pin identification see 1 4 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR R01DS0258EJ0100 Rev 1 00 Page 5 of 74 RENESAS m RL78 G1D CHAPTER 1 OUTLINE 1 4 Pin Identification ANIO to ANIS ANI16 to ANI19 ANT RF AVREFM AVREFP AVss RF CL
45. T a c 4 spens 1 The low level is input to the TOOLO pin 2 The external reset is released POR and LVD reset must be released before the external reset is released 3 The TOOLO pin is set to the high level 4 Setting of the flash memory programming mode by UART reception and complete the baud rate setting Remark 1 Communication for the initial setting must be completed within 100 ms after the external reset is released during this period tsu Time to release the external reset after the TOOLO pin is set to the low level tHD Time to hold the TOOLO pin at the low level after the external reset is released excluding the processing time of the firmware to control the flash memory RO1DS0258EJ0100 Rev 1 00 Page 73 of 74 RENESAS m RL78 G1D 3 PACKAGE DRAWINGS 3 PACKAGE DRAWINGS 48 pin plastic WQFN 6 x 6 JEITA Package Code RENESAS Code Previous Code MASS Typ g P HWQFNA8 6x6 0 40 PWQNO0048LB A 0 07 Unit mm D 36 25 37 24 Index area 48 13 1 12 F S lt lt suuuuumsununmuurmes HI EJ 11 Detail F 8 1 gt 12
46. Unit number m 0 1 n Channel number 0 1 9 and POM numbers g 0 1 2 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number 00 02 11 R01DS0258EJ0100 Rev 1 00 Page 33 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 5 During communication at same potential CSI mode slave mode SCKp external clock input supporting CSIOO and CSI20 Ta 40 to 85 C 1 6 V lt Voo Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed 15 low speed main LV low voltage main Mode Mode main Mode MIN MAX MIN MAX MIN MAX SCKp cycle time 2 7 V lt lt fuck gt 16 MHz 8 dd 3 6 V fuck lt 16 MHz 6 G fuck 6 fuck 2 4 V lt Voo lt 3 6 V 6 fuck G fuck 6 fuck and Soo and 500 and 500 1 8 V lt Voo lt 3 6 V 6 fuck 6 fuck and and 750 750 1 6 V lt Voo lt 3 6 V G fuck and 1500 SCKp high low 2 7 V lt Voo lt 3 6 V tkcy2 2 8 tkcy2 2 8 tkcv2 2 8 level width 2 4 V lt Voo lt 3 6 V tkcy2 2 tkcy2 2 tkcy2 2 18 18 1 8V lt Vo0 lt 3 6V 2 2 18 18 1 6 V lt Voo lt 3 6 V 2 2 66 Slp setup time 2 7 V lt Voo lt 3 6 V 1 1 1 to SCKpT 20 30 30 2 4 lt lt 3 6 V 1
47. V 405 0 4 405 Q4 405 ns 1 6 V lt lt 2 0 V C 100 pF Re 5 5 1 8 V lt Voo lt 3 3 V E 044 405 0444 405 ns 1 6V Vo lt 2 0 V 100 pF 5 5 Notes1 The value must also be 4 or lower 2 Use it with Voo Vb 3 Set the fuck value to keep the hold time of SCLr L and SCLr Caution Select the TTL input buffer and the N ch open drain output tolerance mode for the SDAr and the N ch open drain output tolerance mode for the SCLr pin by using port input mode register g PIMg and port output mode register POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the page after the next page R01DS0258EJ0100 Rev 1 00 Apr 24 2015 ztENESAS Page 52 of 74 RL78 G1D 2 ELECTRICAL SPECIFICATIONS Simplified C mode connection diagram during communication at different potential SDAr RL78 ser device microcontroller U SCLr Simplified mode serial transfer timing during communication at different potential 1 fscL tLow SCLr SDAr tHD DAT tsu DAT Remarks 1 Re O Communication line SDAr SCLr pull up resistance Ce F Communication line SDAr SCLr load capacitance Ve V Communication line voltage 2 r number 00 10 g PIM POM number 9 0 1 3 fuck Serial ar
48. V voltage HS high speed main Mode Notes 1 2 10 bit resolution 1 8 V lt Voo lt 3 6 V Zero scale error 1 6 V lt Voo lt 3 6 V 10 bit resolution 1 8 V lt Voo lt 3 6 V 1 6 V lt Voo lt 3 6 V Full scale error Integral linearity error 10 bit resolution 1 8 V lt Voo lt 3 6 V 1 6 V lt Voo lt 3 6 V Differential linearity error 10 bit resolution 1 8 V x Voo lt 3 6 V 1 6 V lt Voo x 3 6 V Analog input voltage ANIO to ANI3 ANI16 to ANI17 Note 4 Select internal reference voltage 2 4 V Vop lt 3 6 V HS high speed mode Note 4 Select temperature sensor output voltage 525 2 4 V lt 3 6 V HS high speed mode Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 When the the conversion time is set to 57 us min and 95 us max 4 Referto 2 8 2 Temperature sensor and internal reference voltage characteristics R01DS0258EJ0100 Rev 1 00 Page 60 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 4 When reference voltage Internal reference voltage ADREFP1 1 ADREFPO 0 reference voltage AVnEFW ANI1 ADREFM 1 conversion target ANIO to ANI3 ANI16 to ANI19 Ta 40 to 85 C 2 4 V lt Voo Voo nr nr lt 3 6 V Vss Vss nr AVss nr
49. and VIH MIN 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device 3 PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to
50. be taken for PW boards with mounted semiconductor devices 4 STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunct
51. ck Notes 1 clock oscillator fxr 1 6 V lt Vio lt 3 6 V 32 768 kHz External subsystem clock 1 6 V lt lt 3 6 V 32 768 kHz Indicates only permissible oscillator frequency ranges Refer to AC Characteristics for instruction execution time Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics 2 This mode is prohibited to use in case of using DC DC converter R01DS0258EJ0100 Rev 1 00 Apr 24 2015 ztENESAS Page 13 of 74 RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 3 Oscillator Characteristics 2 3 1 X1 XT1 XRF oscillator characteristics Ta 40 to 85 C 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V X1 clock oscillation Ceramic resonator 2 7 V lt Voo lt 3 6 V 20 m frequency Crystal resonator 1 8 V lt Voo lt 2 7 V Pa a me epe RF base clock oscillation frequency Note 2 accuracy Notes 1 Indicates only permissible oscillator frequency ranges Refer to AC Characteristics for instruction execution time Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics 2 This Oscillator characteristics is base clock for RF Transceiver Caution Since the CPU is started by the high speed on chip oscillator clock after a reset r
52. ck value to keep the hold time of SCLr L and SCLr H Caution Select the normal input buffer and the N ch open drain output tolerance mode for the SDAr and the normal output mode for the SCLr pin by using port input mode register g PIMg and port output mode register h POMh Remarks are listed on the page after the next page R01DS0258EJ0100 Rev 1 00 Page 38 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS Simplified mode mode connection diagram during communication at same potential in SDAr SDA RL78 microcontroller User device SCLr SCL Simplified C mode serial transfer timing during communication at same potential 1 fsc SCLr SDAr tHD DAT tsu DAT Remarks 1 Rb Q Communication line SDAr pull up resistance Communication line SDAr SCLr load capacitance 2 r number 00 20 g PIM number g 1 h POM number h 1 3 Serial array unit operation clock frequency Operation clockw to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number 0 1 n Channel number n 0 mn 00 02 RO1DS0258EJ0100 Rev 1 00 Page 39 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 7 Communication at different potential 1 8 V 2 5 V UART mode Ta 40 Parameter Transfer rate Notes 1 2 3 to 85 C 2 4 V lt nr
53. e Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Vivito Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Power supply fall time Minimum pulse width Detection delay time R01DS0258EJ0100 Rev 1 00 Page 63 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS LVD Detection Voltage of Interrupt amp Reset Mode Ta 40 to 85 C 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions Interrupt and VPoce Vroco 0 0 0 falling reset voltage VLvDA1 LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 1 Rising release reset voltage Falling interrupt voltage Vivpas LVIS1 LVISO 0 0 Rising release reset voltage Falling i
54. e above table are applied even when bit 2 PIOR2 in the peripheral redirection register PIOR is 1 At this time the pin characteristics lou must satisfy the values in the redirect destination Remark The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Standard mode Cb 400 pF Rb 2 7 R01DS0258EJ0100 Rev 1 00 Page 55 of 74 RENESAS m RL78 G1D 2 fast mode 2 ELECTRICAL SPECIFICATIONS Ta 40 to 85 C 1 8 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter SCLAO clock frequency Conditions Fast mode 2 7 V lt Voo 3 6V HS high speed main Mode LS low speed main Mode LV low voltage main Mode MAX MAX MAX fck gt 3 5 MHz 2 4 V lt Voo lt 3 6 V 1 8 V lt Voo lt 3 6 V Setup time of restart condition 2 7 V lt Voo 3 6V 2 4 V lt Voo lt 3 6 V 1 8 V lt Voo lt 3 6 V Hold time THD sTA 2 7 V lt Voo lt 3 6 V 2 4 V lt Voo lt 3 6 V 1 8 V lt Voo lt 3 6 V Hold time when SCLAO q 2 7 V lt Voo lt 3 6 V 2 4 V lt Voo lt 3 6 V 1 8 V lt Voo lt 3 6 V Hold time when SCLAO 2 7 V lt Voo 3 6V 2 4 V lt Vom lt 3 6 V 1 8 V lt Voo lt 3 6 V 2 7 V l
55. elease check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register by the user Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register OSTS after sufficiently evaluating the oscillation stabilization time with the resonator to be used 2 3 2 On chip oscillator characteristics Ta 40 to 85 C 1 6 V lt Voo nr AVpp nr lt 3 6 V Vss nr AVss nr 0 V Oscillators Conditions High speed on chip oscillator clock frequency High speed on chip oscillator clock 20 to 85 frequency accuracy 40 to 20 C Low speed on chip oscillator clock fi frequency Low speed on chip oscillator clock frequency accuracy On chip oscillator clock frequency for the funr RF slow clock On chip oscillator clock frequency accuracy fi are for the RF slow clock Notes 1 High speed on chip oscillator frequency is selected by bits O to of option byte 000C2H 010C2H and bits 0 to 2 of HOCODIV register 2 This indicates the oscillator characteristics only Refer to AC Characteristics for instruction execution time 3 This indicates the oscillator characteristics only R01DS0258EJ0100 Rev 1 00 Page 14 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 4 DC Characteristics 2 4 1 Output current Ta 40 t
56. elf programming library 3 This shows the flash memory characteristics This is a result obtained from Renesas Electronics reliability test 2 12 Special Flash Memory Programming Communication UART Ta 40 to 85 C 1 8 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V ransfer rate en programming of flash memory 000 ps T f Wh i f flash 115 200 1 000 000 b R01DS0258EJ0100 Rev 1 00 Page 72 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 13 Timing of Entry to Flash Memory Programming Modes Ta 40 to 85 C 1 8 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions Time to complete the communication for the initial POR and LVD reset must be released setting after the external reset is released before the external reset is released Time to release the external reset after the TOOLO POR and LVD reset must be released pin is set to the low level before the external reset is released Time to hold the TOOLO pin at the low level after POR and LVD reset must be released the external reset is released before the external reset is released excluding the processing time of the firmware to control the flash memory a4 RESET V V 723 us processing time r4 gt 1 byte data for setting mode cfe IN 4 tsuINI
57. ev 1 00 Apr 24 2015 ztENESAS Page 31 of 74 RL78 G1D 2 ELECTRICAL SPECIFICATIONS 3 During communication at same potential CSI mode Internal communication supporting CSI21 only Ta 40 to 85 C 1 6 V lt Voo Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MAX MIN MAX MIN MAX SCKp cycle time gt 2 4 V lt lt 3 6 V Note 2 fcik 1 8V x lt 3 6 V 1 6 V lt Voo lt 3 6 V Note Use the more than 6 5 MHz and lower than 24 MHz Remark This specification is for CSI21 only R01DS0258EJ0100 Rev 1 00 Page 32 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 4 During communication at same potential CSI mode master mode SCKp internal clock output supporting 100 and CSI20 Ta 40 to 85 C 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed main LS low speed LV low voltage Mode main Mode main Mode MIN MAX MIN MAX MIN MAX SCKp cycle time gt 2 7 V Vo lt 3 6 V 1000 4 fo 24V Vo 36 V 1000 1 8 V lt Voo lt 3 6 V 1000 1 6 V lt Voo lt 3 6 V 1000 SCKp high low 2 7 V lt Voo lt 3 6 V tkcvi 2 1 2 1 2 level width 18 50 50
58. f alternate function pins are the same as those of the port pins AVner 9 Side reference voltage of the A D converter Reference voltage is Vss R01DS0258EJ0100 Rev 1 00 Apr 24 2015 Page 12 of 74 ztENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 2 Operating Voltage Ta 40 to 85 Voo Rr AVpp nr Vss Vss AVss nr 0 V Clock generator Main system clock High speed on chip oscillator Flash operation mode HS high speed main mode Operation voltage 2 7 V lt Voo lt 3 6 V CPU operation clocks 4 1 1 MHz to 32 MHz 2 4 V lt Voo lt 2 7 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt 0 lt 3 6 V 1 MHz to 8 MHz Note 2 LV low voltage main mode 1 6 V lt Vio lt 3 6 V 1 MHz to 4 MHz X1 clock oscillator fx HS high speed main mode 2 7 V lt Voo lt 3 6 V 1 MHz to 20 MHz LS low speed main mode 1 8 V lt Vio lt 3 6 V 1 MHz to 8 MHz Note 2 LV low voltage main mode 1 6 V lt Voo lt 3 6 V 1 MHz to 4 MHz External main system clock fex HS high speed main mode 27 V lt Voo lt 3 6 V 1 MHz 20 MHz 2 4 V lt Voo lt 2 7 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt Vio lt 3 6 V 1 MHz to 8 MHz Note 2 LV low voltage main mode 1 6 V lt Voo lt 3 6 V 1 MHz to 4 MHz Subsystem clo
59. fied otherwise the measurement is performed by our evaluation board 25 Voo nr AVpp nr 3 0 V F 2440 MHz Vss Vss nr AVss 0 V Parameter Conditions RF frequency range RFcr 2402 2480 MHz Data rate RFoata 1 Mbps Maximum transmitted RFrower RF output pin RF low power mode 18 15 12 dBm output power RF normal mode 3 0 3 dBm RF high performance 3 0 3 dBm mode Transmitted output 0 1 2 7 10 15 dBm 15 0 dBm power setting Spurious radiation RFrxsp 30 to 88 MHz 76 55 dBm 88 to 216 MHz 76 52 dBm 216 to 960 MHz 74 49 dBm 960 to 1000 MHz 74 30 dBm 1to 12 75 GHz 42 41 dBm 1 8 to 1 9 GHz 73 47 dBm 5 15 to 5 3 GHz 71 47 dBm Harmonics 1 2 Harmonics 52 41 dBm 3 Harmonics 51 41 dBm Frequency tolerance RFrxrerr 30 30 ppm Impedance RFz 50 0 Q Caution Install EMI countermeasures as required to prevent EMI effects of the RF transmission characteristics R01DS0258EJ0100 Rev 1 00 Page 65 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 9 2 RF reception characteristics Unless specified otherwise the measurement is performed by our evaluation board 25 Voo nr AVpp nr 3 0 V F 2440 MHz Vss Vss nr AVss 0 V Parameter Conditions RF input frequency RFnxrRIN MHz Maximum input level RF eve
60. he next page R01DS0258EJ0100 Rev 1 00 Page 47 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 10 Communication at different potential 1 8 V 2 5 V CSI mode slave mode SCKp external clock input 2 2 Ta 40 to 85 C 1 8 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed 15 low speed main LV low voltage main Mode Mode main Mode MIN MAX MIN MAX MIN MAX SCKp high low level 2 7 V lt Voo lt 3 6 V 2 2 width 2 3 V lt lt 2 7 V 18 50 2 4 V lt lt 3 3 V tkcy2 2 1 6 lt x2 0V 50 1 8 V lt Vpp 3 3 V 1 6 V lt Vb lt 2 0 V 50 50 Slp setup time 2 7 V lt Voo lt 3 6 V 1 fmck 1 to SCKpt 2 3 V lt lt 4 0 V 20 30 30 2 4 V lt lt 3 3 V 1 1 1 fuck 1 6 V lt lt 2 0 V 30 30 30 1 8 xVpp 3 3 V 1 1 fuck 1 6 V lt Vb lt 2 0 V 30 30 51 hold time 2 7 V lt lt 3 6 V 1 fuck 31 1 fuck 1 fuck from 23V Vs 4 0 V 81 31 24VxVpp 3 3 V 1 fuck 31 1 fuck 1 fuck 16V lt Vb lt 2 0V 31 31 1 8 lt Vop lt 3 3 V 1 1 fuck 1 6 V lt Vb lt 2 0 31 31 Delay time from SCKp 2 7 V lt Voo lt 3 6 V 2 2 2 to SOp output 2 3 lt lt 2 7 214 573 573 Cb 30 pF Re 2
61. ified mode 2 2 Ta 40 to 85 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX Data setup time reception tsu pat 2 7 V lt lt 3 6 V 1 fwck 1 1 fuck C 50 pF R 2 7kQ 85 145 145 Note2 Note2 2 4 V x Voo lt 3 6 V 1 fuck 1 fuck 1 fuck C 100 pF Rb 3 145 145 145 Note2 Note2 Note2 1 8 V lt Voo lt 3 6 V 1 fuck 1 fuck Cb 100 pF Re 3 145 145 Note2 Note2 2 4 V x Voo lt 2 7 V 1 fuck 1 fuck 1 fuck Cs 100 pF 5 230 230 230 Note2 Note2 Note2 1 8 V lt Voo lt 2 7 V 1 fuck 1 fuck C 100 pF Re 5 230 230 Note2 Note2 1 6 V x lt 1 8 V 1 fuck 100 pF 5 kO 290 Note2 Data hold time transmission 2 7 V lt lt 3 6 V 0 50 pF Rb 2 7 kO 2 4 V lt Voo 3 6 V Cb 100 pF Rb 1 8 V lt Voo lt 3 6 V Cb 100 pF Rb 3 2 4 V lt lt 2 7 V 0 405 0 405 0 405 ns C 100 pF Ro 5 1 8 V lt Voo lt 2 7 V 0 405 0 405 ns C 100 pF Ro 5 1 6 V lt 1 8 V 0 405 ns C 100 pF Re 5 Notes 1 The value must also be 4 or lower 2 Set the fu
62. in Mode LS low speed main Mode LV low voltage main Mode MIN MAX 83 3 MIN MAX 250 MIN MAX 500 SCKp high low level width tkcvi 2 10 tkcvi 2 50 tkcvi 2 50 setup time to SCKpT Note 1 33 110 110 hold time from 5 Note 1 10 10 10 Delay time from SCKp to SOp output 20 pF Note 3 Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The time becomes to SCKpV when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpf when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 Cis the load capacitance of the SCKp and SOp output lines Cautions Select the normal input buffer for the and the normal output mode for the SOp and SCKp pin by using port input mode register g PIMg and port output mode register g POMg Remarks 1 This specification is valid only when CSIOO s peripheral I O redirect function is not used 2 p CSI number 00 m Unit number m 0 n Channel number 0 9 and POM numbers g 1 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 R01DS0258EJ0100 R
63. ion and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 2 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 3 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Rene
64. l 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2015 Renesas Electronics Corporation All rights reserved Colophon 5 0
65. lectronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics 6 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any o
66. lock oscillation frequency 4 Except subsystem clock operation temperature condition of the value is TA 25 R01DS0258EJ0100 Rev 1 00 Page 20 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 Standby current Ta 40 to 85 C 1 6 V lt Voo Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HALT HS high speed fin 32 MHz Von 3 0 V Note 7 current main mode fiu 24 MHz Von 3 0 V Note 1 2 16 MHz Voo 3 0 LS low speed 8 MHz 3 0 V Note 7 main mode Voo 2 0 V LV low voltage 4 MHz Voo 3 0 V Note 7 main mode Voo 2 0 V HS high speed fmx 20 MHz 3 0 V main mode fmx 10 MHz Voo 3 0 VN LS low speed fux 8 MHz Voo 3 0 V main mode Voo 2 0 V Subsystem clock fsus 32 768kHz Ta 40 operation Ta 4257 C n 50 70 Ta 85 STOP 40 C current 5 TA 425 C TA 50 C 70 C Ta 85 C Notes and Remarks are listed on the next page RO1DS0258EJ0100 Rev 1 00 Page 21 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS Notes 1 Current flowing into including the input leakage current flowi
67. lower row apply respectively when the DC DC converter embedded in the RF chip is and is not in use R01DS0258EJ0100 Rev 1 00 Page 24 of 74 RENESAS m RL78 G1D 2 6 AC Characteristics 2 ELECTRICAL SPECIFICATIONS Ta 40 to 85 C 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Cycle time minimum instruction execution time Conditions Main system HS high speed 2 7 V Vox 3 6V 0 03125 clock main mode 24VxVp 27V 0 0625 operation LV low voltage main mode 0 25 LS low speed main mode 0 125 Subsystem clock fsus operation 28 5 In the self HS high speed 2 7 V lt Vo lt 3 6 V 0 03125 programming main mode 2 4 V lt Vo lt 2 7 V 0 0625 mode LV low voltage mai n mode 0 25 LS low speed main mode 0 125 External clock frequency 2 7 V lt Vo lt 3 6 V 1 20 2 4 V lt Vo lt 2 7 V 1 16 1 8 V lt Voo 24V 1 8 EXCLKS 32 35 EXSLK_RF When 32 768 kHz input 500 ppm 32 751616 32 768 32 784384 When 16 384 kHz input 500 ppm 16 375808 16 384 16 392192 External clock input high level width low level width 2 7 V lt lt 3 6 V 24 2 4 lt 27V 30 1 8 V lt Voo 24V 60 texus texts EXCLKS 13 7 tExHRF TEXLRF EXSLK_R
68. ne voltage 2 q UART number q 0 1 g PIM and POM number 9 0 1 R01DS0258EJ0100 Rev 1 00 Page 41 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 8 Communication at different potential 2 5 V CSI mode master mode SCKp internal clock output supporting CSIOO only Ta 40 to 85 C 2 7 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter SCKp cycle time Conditions tkcy1 gt 2 fcik 2 7 V lt Voo lt 3 6 V 2 3 lt lt 2 7 V C 20 pF Rb 2 7 HS high speed main Mode LS low speed main Mode LV low voltage main Mode MIN MAX MIN MAX MIN MAX SCKp high level width 27 V lt Voo lt 3 6 V 2 3 V lt lt 2 7 V C 20 pF Rb 2 7 tkcvi 2 120 tkcvi 2 120 tkcvi 2 120 SCKp low level width 2 7 V lt Voo lt 3 6 V 2 3 V lt lt 2 7 V Co 20 pF Rb 2 7 tkcvi 2 10 tkcvi 2 50 tkcvi 2 50 51 setup time to SCKpT 27 V lt lt 3 6 V 2 3 V lt Vo lt 2 7 V Co 20 pF Rb 2 7 51 hold time from SCKpf 2 7 V lt Voo lt 3 6V 2 3 V lt lt 2 7 V Co 20 pF Rb 2 7 Delay time from tkso1 2 7 V lt lt 3 6 V 130 130 130 ns SCKpi to SOp 2 8V Ve 2 7 V Note 1 output 20 pF Rb 2 7 51 setup time tsiki 2 7 V lt Voo lt 3 6 V
69. ned e 16 bits x 16 bits 32 bits 32 bits Unsigned or signed Serial interface e CSI 2 channels e UART 2 channels e l C Simplified C channels Timer e 16 bit timer 8 channels e 12 bit interval timer 1 channel e Real time clock 1 channel calendar for 99 years alarm function and clock correction function e Watchdog timer 1 channel operable with the dedicated low speed on chip oscillator A D converter e 8 10 bit resolution A D converter Voo 1 6 to 3 6 V e Analog input 8 channels Note e Internal reference voltage 1 45 V and temperature sensor port e I O port 32 e Can be set to N ch open drain TTL input buffer and on chip pull up resistor e Different potential interface Can connect to a 1 8 2 5 V device e On chip clock output buzzer output controller RO1DS0258EJ0100 Rev 1 00 Page 2 of 74 RENESAS m RL78 G1D CHAPTER 1 OUTLINE Others e On chip BCD binary coded decimal correction circuit Note Can be selected only in HS high speed main mode e ROM RAM capacities Flash ROM Data Flash RL78 G1D R5F11AGG R5F11AGH R5F11AGJ Note 19 KB when the self programming function is used R01DS0258EJ0100 Rev 1 00 Apr 24 2015 ztENESAS Page 3 of 74 RL78 G1D CHAPTER 1 OUTLINE 1 2 List of Part Numbers Figure 1 1 Part Number Memory Size and Package of RL78 G1D Part No R5F11AGGAxxxNB 20 Packing 20 Tray 40 Embossed Tape
70. ng when the level of the input pin is fixed to Voo or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit port and on chip pull up pull down resistors and the current flowing during data flash rewrite 2 During HALT instruction execution by flash memory 3 When high speed on chip oscillator and subsystem clock are stopped 4 When high speed system clock and subsystem clock are stopped 5 When high speed on chip oscillator and high speed system clock are stopped When setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog timer Not including the current flowing into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Voo x 3 6 V 1 MHz to 32 MHz 2 4 V lt Voo lt 3 6 VO 1 MHz to 16 MHz LS low speed main mode 1 8 V lt Voo x 3 6 V8 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt Voo lt 3 6 V8 1 MHz to 4 MHz If operation of the subsystem clock when STOP mode same as when HALT mode of subsystem clock operation 9 The upper value is for square wave input and the lower is with an oscillator connected Remarks 1 fmx High speed system cl
71. nsitivity vs 178 610 Voltage in RF Reception 86 _ gt ee ax z v 96 5 98 100 16 18 2 22 24 28 0228 32 34 86 38 Voltage V RO1DS0258EJ0100 Rev 1 00 Page 71 of 74 Apr 24 2015 RENESAS a RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 10 RAM Data Retention Characteristics 40 to 85 Note The value depends on the POR detection voltage When the voltage drops the data is retained before POR reset is effected but data is not retained when a POR reset is effected e 1 STOP mode lt Operation mode RAM data retention Vpp 4 STOP instruction execution Standby release signal interrupt request 2 11 Flash Memory Programming Characteristics Ta 40 to 85 C 1 8 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions CPU peripheral hardware clock 1 8 V lt Voo lt 3 6 V frequency Number of code flash rewrites Retained for 20 years Ta 85 C Notes 1 2 3 Number of data flash rewrites Retained for 1 year Ta 25 1 000 000 Notes 1 2 3 Retained for 5 years Ta 85 C 100 000 Retained for 20 years Ta 85 C 10 000 Notes 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite 2 When using flash memory programmer and Renesas Electronics s
72. nsor output voltage Vrmeses Setting ADS register 80H 25 Internal reference voltage Setting ADS register 81H Temperature coefficient Temperature sensor output voltage that depends on the temperature Operation stabilization wait time 2 8 3 POR circuit characteristics Ta 40 to 85 Vss nr AVss nr 0 V Parameter Conditions Detection voltage Rise time Fall time Minimum pulse width Other than STOP SUB RUN SUB HALT Note This is the time required for the POR circuit to execute a reset operation when Vo falls below When the main system clock has been stopped by setting bit O HIOSTOP and bit 7 MSTOP of the clock operation status control register CSC or when the microcontroller enters STOP mode this is the time required for the POR circuit to execute a reset operation between when falls below 0 7 V and when rises to Vron or higher TPw Supply voltage Vpp Vprpn or 0 7 V R01DS0258EJ0100 Rev 1 00 Page 62 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 8 4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode Ta 40 to 85 lt nr AVpp nr lt 3 6 V Vss nr AVss nr 0 V Parameter Conditions Detection Supply voltage Power supply rise time voltage Power supply fall tim
73. nternal clock output supporting 100 and CSI20 1 2 Ta 40 to 85 C 1 8 V lt Voo Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX SCKp cycle time tkcv 2 7 V lt Voo x 3 6 V 23VsV x2 7V C 30 pF Ro 2 7 2 4 V lt lt 3 3 1 6 V lt lt 2 0 Co 30 pF Ro 5 5 1 8 V lt lt 3 3 V 1 6 V lt Vb lt 2 0 v 30 pF 5 5 KQ SCKp high level 2 7 V lt Voo lt 3 6 V 2 3 V lt Vox 2 7 V tkcvi 2 2 2 width Cb 30 pF Rb 2 7 170 170 170 2 4 V lt lt 3 3 V 1 6 V lt Vbo lt 2 0 tkcvi 2 2 2 Cb 30 pF Rb 5 5 458 458 458 1 8 V lt lt 3 3 V 1 6 V lt Vb lt 2 0 V tkcvi 2 tkcvi 2 Cb 30 pF Rb 5 5 458 458 SCKp low level 2 7 V lt Voo lt 3 6 V 2 3 V x Vo lt 2 7 V tkcvi 2 tkcvi 2 tkcvi 2 width C pF Ro 2 7 18 50 50 2 4 V lt 3 3 V 1 6 V lt Vbo lt 2 0 V tkcvi 2 tkcvi 2 tkcvi 2 Cb 30 pF Rb 5 5 50 50 50 1 8 V lt lt 3 3 V 1 6 V lt Vb lt 2 0 V tkcvi 2 tkcvi 2 Cb 30 pF Rb 5 5 50 50 setup time tsi 2 7 V lt Voo lt 3 6 V 2 3 V lt lt 2 7 V 1 to SCKpT C 30 p
74. nterrupt voltage VivpBo VPoce 1 Vroco 0 0 1 falling reset voltage Vivos1 LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage Vivps2 LVIS1 LVISO 0 1 Rising release reset voltage Falling interrupt voltage VivpB3 LVIS1 LVISO 0 0 Rising release reset voltage Falling interrupt voltage Vivpco VPeoce Vroco 0 1 0 falling reset voltage Vivoc1 LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 1 Rising release reset voltage Falling interrupt voltage Vivppo VPoce Vroco 0 1 1 falling reset voltage Vivoo1 LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage VLvpp2 LVIS1 LVISO 0 1 Rising release reset voltage lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Falling interrupt voltage 2 8 5 Supply voltage rise time Ta 40 to 85 C Vss Vss AVss 0 V em PS Ls we Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until Voo reaches the operating voltage range shown in 2 5 AC Characteristics R01DS0258EJ0100 Rev 1 00 Page 64 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 9 RF Transceiver Characteristics 2 9 1 RF transmission characteristics Unless speci
75. o 85 C 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Output current high Conditions POO P01 P02 P10 P11 P12 1 6 V lt Voo lt 3 6 V 10 0 P13 P14 P15 16 P30 40 P120 P130 P140 P147 P01 P02 P40 P120 P130 P140 Total 2 7 V lt Voo x 3 6 V 1 8 V lt lt 2 7 V 1 6 V lt Vpp lt 1 8 V 27 V Vop lt 3 6 V 1 8 V lt lt 2 7 V 1 6 V lt Vpp lt 1 8 V 1 6 V lt lt 3 6 V 5 0 2 5 P10 P11 P12 P13 P14 P15 P16 Total P30 P147 19 0 10 0 5 0 m 35 0 Note 3 Total of all pins P20 P21 P22 P23 1 6 V lt Voo lt 3 6 V 0 1 1 6 V lt Voo lt 3 6 V 1 6 V lt lt 3 6 Total 1 5 GPIOO GPIO1 GPIO2 GPIO3 Per pin 2 0 Output current 0 91 Notes 1 POO P01 P02 P10 P11 P12 1 6 V lt lt 3 6 V 20 0 P13 P14 P15 P16 P30 P40 P120 P130 P140 P147 P60 P61 P01 P02 P40 P120 P130 P140 Per pin 15 Qe 15 0 1 6 V lt lt 3 6 V 2 7 V lt lt 3 6 1 8 V lt Voo lt 2 7 V 1 6 V lt Vpp 1 8 V 2 7 V lt lt 3 6 V 1 8 V lt Voo lt 2 7 V 1 6 V lt lt 1 8 V 1 6 lt lt 3 6 V 1 6 V lt lt 3 6 V 1 6 V lt lt 3 6 1 6 V lt l
76. o nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX SCLr clock frequency 27N Vop lt 3 6 V 1000 300 300 kHz Note 1 Note 5 Note 5 2 3 V lt lt 2 7 V 50 pF Rb 2 7 2 7 V lt Voo 3 6 V 400 300 300 kHz Note 1 Note 5 Note 5 2 3 V lt lt 2 7 V C 100 pF Rb 2 7 2 4 V lt Voo lt 3 3 V 300 300 300 kHz Note 1 Note 1 Note 1 1 6 V lt lt 2 0 V 100 pF Rb 5 5 1 8 V lt Voo lt 3 3 V 300 300 kHz Note 1 Note 1 1 6 V lt Vb lt 2 0 100 pF Rb 5 5 Hold time when SCLr 2 7 lt lt 3 6 475 1550 1550 ns Y 2 3 V lt lt 2 7 V Cp 50 pF Rb 2 7 2 7 lt lt 3 6 1150 1550 1550 ns 2 3 V lt V lt 2 7 V 100 pF 2 7 KQ 2 4 lt lt 3 3 V 1150 1550 1550 ns 1 6 V lt Vb lt 2 0 V 100 pF 5 5 1 8 V lt Voo lt 3 3 V 1550 1550 ns 1 6 V lt Vb lt 2 0 V 100 pF 5 5 Hold time when SCLr 2 7 lt lt 3 6 V 200 610 610 ns Mr 2 3 V lt lt 2 7 V Cp 50 pF Rb 2 7 2 7 V lt lt 3 6 V 600 610 610 ns 2 3V Vo x27 V C 100 pF Re 2 7 2 4 V lt Voo lt 3 3 V 610 610 610 ns 16 lt lt 2 0 C 100 pF Rb 5 5
77. ock frequency External main system clock frequency 2 High speed on chip oscillator clock frequency 3 Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation and STOP mode temperature condition of the value is TA 25 R01DS0258EJ0100 Rev 1 00 Page 22 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 3 Current for each peripheral circuit Ta 40 to 85 C 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions Note 1 Low speed on chip oscillator operating current Notes 1 2 3 RTC operating IRrc current Notes 1 2 4 12 bit interval timer operating current Watchdog timer 9989 25 fi is 15 kHz operating current Notes 1 6 A D converter When conversion at AVnerP 3 0 V operating current maximum speed Note 1 A D converter ADREF reference voltage current Note 1 Thermometer sensor ITmPs operating current Note 1 7 LVD operating lvi current Notes 1 9 Flash self IFsP programming operating current Notes 1 8 BGO current Note 10 SNOOZE operating Isnoz ADC operation The mode is performed current The A D conversion operations are performed Low voltage mode AVnerP Voo 3 0 V CSI UART operation Notes 1 Current flowing to
78. onditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX SCLAO clock frequency Fast mode plus 2 7 V lt Voo lt 3 6 V gt 10 MHz Setup time of restart 2 7 lt Voo lt 3 6 V condition Hold time 2 7 V lt Voo lt 3 6 V Hold time when SCLAO 2 7 V lt Voo 3 6V 4 Hold time when SCLAO 2 7 V lt Voo lt 3 6 V Data setup time 2 7 V lt Voo lt 3 6 V reception Data hold time tHD DAT 2 7 lt Voo lt 3 6 V transmission Setup time of stop tsusto 27V lt Voo lt 3 6 condition Bus free time 2 7 V lt Voo lt 3 6V Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution The values in the above table are applied even when bit 2 PIOR2 in the peripheral redirection register PIOR is 1 At this time the pin characteristics must satisfy the values in the redirect destination Remark The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Fast mode plus Cb 120 pF Rb 1 1 serial transfer timing SCLAn THD STA SDAAn Stop
79. ray unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 02 R01DS0258EJ0100 Rev 1 00 Page 53 of 74 Apr 24 2015 ztENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS 2 7 2 Serial interface IICA 1 C standard mode Ta 40 to 85 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MAX SCLAO clock frequency fsc Standard 2 7 V lt Voo 3 6 V 0 100 0 100 0 100 kHz de MHz 2 4 V lt lt 3 6 V 0 100 0 100 0 100 kHz 1 8 V lt Voo lt 3 6 V 0 100 0 100 kHz 1 6 V lt Voo lt 3 6 V 0 100 kHz Setup time of restart tsu sTA 2 7 V lt Voo lt 3 6 V 4 7 4 7 4 7 8 condition 24V x Vo x 3 6 V 47 47 4 7 us 1 8 V lt Voo lt 3 6 V 4 7 4 7 LS 1 6 V lt Voo lt 3 6 V 47 LS Hold time tHo sta 2 7 V lt Voo lt 3 6 V 4 0 4 0 4 0 us 2 4 V lt lt 3 6 4 0 4 0 4 0 us 1 8 V lt Voo lt 3 6 V 4 0 4 0 Lus 1 6 V lt lt 3 6 V 4 0 LS Hold time when SCLAO 2 7 V lt Voo lt 3 6 V 4 7 4 7 4 7 HS D 2 4 V lt Voo lt 3 6 V 4 7 4 7 4 7 us 1 8 V lt Voo lt 3 6 V 4 7 4 7 Lus
80. register g POMg Remarks 1 p CSI number 00 20 m Unit number m 0 1 n Channel number n 0 9 PIM and POM numbers g 1 2 Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 10 CSI mode connection diagram during communication at same potential SCKp SCK RL78 microcontroller SO User device SOp Sl R01DS0258EJ0100 Rev 1 00 Page 35 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing during communication at same potential When DAPmn 0 and 0 or DAPmn 1 and CKPmn 1 1 2 tku 2 tkH1 2 SCKp tsik1 2 tksn 2 lt 51 tkso1 2 CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcy1 2 SCKp tsiki 2 tksi1 2 51 Remarks 1 CSI number 00 10 21 2 Unit number n Channel number 00 02 11 R01DS0258EJ0100 Rev 1 00 Page 36 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 6 During communication at same potential simplified mode 1 2 Ta 40 to 85 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions HS high speed LS low
81. rol Power supply Power Supply for RF Ground Ground for RF Crystal oscillator Main system clock Crystal oscillator Subsystem clock Crystal oscillator RF clock R01DS0258EJ0100 Rev 1 00 Apr 24 2015 ztENESAS Page 6 of 74 RL78 G1D CHAPTER 1 OUTLINE 1 5 Block Diagram TIMER ARRAY PORT 0 4 to UNIT 8ch Ay gt 00 TOO0 PO1 PORT K Z P10 to P16 TIO1 TOO1 P16 e temen T MER TIO2 TOO2 P15 QD PORT 3 P30 TIO3 TOO3 P14 PORT 4 P40 TIO4 TOO4 P13 TIO5 TOO5 P12 CIL PORT 6 _2 gt P60 P61 TIO6 TOO6 P1 1 CD PORT 7 120 07 07 10 CODE FLASH MEMORY i GU p 4 P121 to P124 DATA FLASH MEMORY meric P130 WINDOW P137 WATCHDOG PORT 14 27 P140 P147 LOW SPEED ON CHIP 122 BIT INTERVAL lt gt ANIO P20 to OSCILLATOR TIMER 2 REAL TIME ANI16 P03 ANI17 P02 A D CONVERTER ANI18 P147 ANI19 P120 RTC1HZ P30 CLOCK 2 REFP 21 SERIAL ARRAY UNITO 4ch POWER ON POR LVD RxDO P14 RESET VOLTAGE CONTROL TxDO P12 DETECTOR RxD1 P03 SERIAL SCLAO P60 SCLAO P14 TxD1 P02 INTERFACE IICAO SDAAO P61 SDAAO P13 RESET CONTROL SCKO0 P10 100 11 000 12 BUZZER OUTPUT SCLOO P10 MEME lt ON CHIP DEBUG TOOLO P40 SDAOO0 P1 1 OUTPUTCONTROL SYSTEM
82. rrent including that for the MCU current flowing into the Vbp pin and that for the RF unit current flowing into the nr AVpp nr pins The characteristics of the MCU current flowing into the Voo pin are given in 2 5 1 and the characteristics of the RF unit current flowing into the RF AVpp nr pins are given in 2 5 2 2 5 1 MCU 1 Operating current Ta 40 to 85 C 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions Operating HS high Basic operation fiu 32 MHz Voo 3 0 V current speed main Normal operation fin 32 2 Voo 3 0 V ca 24 MHz Voo 3 0 V 16 MHz Voo 3 0 V LS low speed operation fia 8 MHz Voo 3 0 V main mode Voo 2 0 V Note 5 LV low Normal operation fin 4 MHz Voo 3 0 V voltage main Von 2 0 V mode 5 Tu HS high Normal operation fmx 20 MHz 3 0 V speed main mode fmx 10 MHz Voo 3 0 999 LS low speed Normal operation fmx 8 MHz Voo 3 0 999 main mode Note 5 Voo 2 0 Subsystem Normal operation fsus 32 768 kHz TA 40 clock operation Ta 425 C n Ta 4509 C Ta 4709 C 85 C Note 6 Notes and Remarks are listed on the next page RO1DS0258EJ0100 Re
83. s RESET RESET RF internal pin low RSTLRF RESET_RF internal pin level width Minimum Instruction Execution Time during Main System Clock Operation Tcv vs HS high speed main mode 10 1 0 When the high speed on chip oscillator clock is selected During self programming When high speed system clock is selected Cycle time Tcv u s 0 1 0 0625 0 05 0 03125 0 01 0 10 20 30 Supply voltage Voo V R01DS0258EJ0100 Rev 1 00 Page 26 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS Tcv vs LS low speed main mode 10 2 1 0 e When the high speed on chip oscillator clock is selected E During self programming v When high speed system clock is selected ES 0 12 0 1 0 01 Supply voltage Von V Tcv vs LV low voltage main mode 10 1 0 i When the high speed on chip oscillator clock is selected During self programming ER When high speed system clock is selected Y 9 0 25 0 1 0 01 Supply voltage Von V R01DS0258EJ0100 Rev 1 00 Page 27 of 74 Apr 24 2015 RENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS AC Timing Test
84. sas Electronics or others 4 You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product 5 Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas E
85. speed LV low voltage main Mode main Mode main Mode MIN MIN MAX SCLr clock frequency 2 7 V lt Voo lt 3 6 V 50 pF Rb 2 7 2 4 V lt 3 6 V 100 pF Rb 1 8 V lt Voo lt 3 6 V Cb 100 pF Ro 3 2 4 V lt Voo lt 2 7 V Cb 100 pF Rb 5 1 8 V lt Voo lt 2 7 V 100 pF Rb 5 1 6 V lt Voo lt 1 8 V Cb 100 pF Rb 5 Hold time when SCLr L 2 7 V lt Voo lt 3 6 V 50 pF Rb 2 7 2 4 V lt 3 6 V Cb 100 pF Rb 3 1 8 V lt Voo lt 3 6 V Cb 100 pF Rb 3 2 4 V lt Voo lt 2 7 V Cb 100 pF Rb 5 1 8 V lt Voo lt 2 7 V C 100 pF Rb 5 1 6 V x lt 1 8 V Cb 100 pF Rb 5 Hold time when SCLr 27 V lt Voo lt 8 6 V 50 pF Rb 2 7 2 4 V lt 8 6 V Cb 100 pF Ro 1 8 V lt Voo lt 3 6 V 100 pF Ro 2 4 V lt Voo lt 2 7 V 100 pF Re 5 1 8 V lt Voo lt 2 7 V Cb 100 pF Rb 5 1 6 V lt Voo lt 1 8 V Cb 100 pF Rb 5 Notes Caution and Remarks are listed on the page after the next page R01DS0258EJ0100 Rev 1 00 Page 37 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS 6 During communication at same potential simpl
86. t 3 6 V Total 9 0 4 5 P10 P11 P12 P13 P14 P15 P16 Total P30 P60 P61 P147 35 0 20 0 10 0 Note 3 Total of all pins 150 0 P20 P21 P22 P23 Per pin 0 4 Total 5 0 2 0 GPIOO GPIO1 GPIO2 GPIO3 Per pin Value of current at which the device operation is guaranteed even if the current flows from the pin to an output pin However do not exceed the total current value Specification under conditions where the duty factor 7096 The output current value that has changed to the duty factor 7096 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to Total output current of pins x 0 7 n x 0 01 Example Where n 50 and 10 0 mA Total output current of pins 10 0 x 0 7 50 x 0 01 14 0 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin Product for industrial applications R5F11AGGDNB R5F11AGHDNB R5F11AGJDNB is 100 0 mA Caution and Remark are listed on the next page R01DS0258EJ0100 Rev 1 00 Apr 24 2015 Page 15 of 74 ztENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS Caution P02 P03 and P10 to P15 do not output high level in N ch open drain mode Remark
87. t Voo lt 3 6 V 2 4 V lt Voo lt 3 6 V 1 8 V lt Voo lt 3 6 V 2 7 V lt Voo lt 3 6 V 2 4 V lt Voo lt 3 6 V 1 8 V lt Voo lt 3 6 V 2 7 V lt Voo lt 3 6 V 2 4 V lt Vo lt 3 6 V 1 8 V lt Voo lt 3 6 V 2 7 V lt Voo lt 3 6 V 2 4 V lt Vo lt 3 6 V 1 8 V lt Voo lt 3 6 V Data setup time tsu DAT reception Data hold time transmission tsu sro Setup time of stop condition Bus free time Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution The values in the above table are applied even when bit 2 PIOR2 in the peripheral redirection register PIOR is 1 At this time the pin characteristics lou must satisfy the values in the redirect destination Remark The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Fast mode Cb 320 pF Rb 1 1 R01DS0258EJ0100 Rev 1 00 Apr 24 2015 Page 56 of 74 ztENESAS RL78 G1D 2 ELECTRICAL SPECIFICATIONS 3 fast mode plus Ta 40 to 85 C 2 7 V lt nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter C
88. ta flash 9 Current flowing when operates flash self programming 10 Shift time to the SNOOZE mode is referred User s Manual Hardware Remarks are listed on the next page RO1DS0258EJ0100 Rev 1 00 Page 23 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS Remarks 1 fi Low speed on chip oscillator clock frequency 2 Subsystem clock frequency 3 CPU and peripheral hardware clock frequency 4 Temperature condition of the value is TA 25 2 5 2 RF unit Ta 40 to 85 C 1 6 V lt Voo nr nr lt 3 6 V Vss Vss nr AVss nr 0 V Parameter Conditions Supply Transmission Transmission RF normal mode current peak current output power Note 1 2 0 dBm RF low power mode RF high performance mode 1 Reception peak current RF normal mode RF low power mode RF high performance mode STANDBY current _ SLEEP RF current DEEP SLEEP current RF slow clock externally input through EXSLK RF RF slow clock from on chip oscillator POWER DOWN current RESET RF current IDDRFIL IDLE_RF current loorrsu SETUP HF current Notes 1 Total current flowing into nr and AVpp nr 2 For each item the values in the upper and
89. ther appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you 8 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 9 Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations 10 It is the responsibility of the buyer or distributor of Renesas Electronics products who
90. v 1 00 Page 19 of 74 RENESAS m RL78 G1D 2 ELECTRICAL SPECIFICATIONS Notes 1 Current flowing into including the input leakage current flowing when the level of the input pin is fixed to Voo or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit port and on chip pull up pull down resistors and the current flowing during data flash rewrite 2 When high speed system clock and subsystem clock are stopped e When high speed on chip oscillator and subsystem clock are stopped 4 When high speed on chip oscillator and high speed system clock are stopped When setting ultra low current consumption AMPHS1 1 Not including the current flowing into the RTC 12 bit interval timer and watchdog timer 5 Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Voo lt 3 6 VQ 1 MHz to 32 MHz 2 4 V lt Voo lt 3 6 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt Voo x 3 6 V9 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt Voo lt 3 6 V8 1 MHz to 4 MHz 6 The upper value is for square wave input and the lower is with an oscillator connected Remarks 1 fmx High speed system clock frequency External main system clock frequency 2 High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 c

RL78/G1D Datasheet - Digi-Key

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